Method for fabricating bitline in semiconductor device

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S238000, C438S241000, C438S652000, C257SE21656, C257SE21657, C257SE21658

Reexamination Certificate

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07932168

ABSTRACT:
A method of a fabricating a bitline in a semiconductor device, comprising: forming an interlayer insulation layer that defines a bitline contact hole on a semiconductor substrate; forming a contact layer to fill the bitline contact hole; forming a bitline contact by planarizing the contact layer; forming a bitline stack aligned with the bitline contact; forming a high aspect ratio process (HARP) layer that extends along the bitline stack and the interlayer insulation layer while covering a seam exposed in a side portion of the bitline stack by excessive planarization during formation of the bitline contact; and forming an interlayer gap-filling insulation layer on the HARP layer that gap-fills the entire bitline stack.

REFERENCES:
patent: 6232224 (2001-05-01), Inoue
patent: 6784084 (2004-08-01), Kang et al.
patent: 7098135 (2006-08-01), Chung et al.
patent: 2007/0096202 (2007-05-01), Kang et al.
patent: 2007/0218684 (2007-09-01), Kim
patent: 2008/0081469 (2008-04-01), Kim
patent: 2009/0218610 (2009-09-01), Goo et al.
patent: 2010/0219530 (2010-09-01), Ryu

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