Matching method for designing layout patterns on a photomask...

Details Matching method for designing layout patterns on a photomask... Matching method for designing layout patterns on a photomask...

2011-07-19

2011-07-19

Huff, Mark F (Department: 1721)

Computer-aided design and analysis of circuits and semiconductor

Design of semiconductor mask or reticle

Analysis and verification

C716S053000, C716S054000, C716S055000

Reexamination Certificate

active

07984392

ABSTRACT:
The present invention relates to a matching method of pattern layouts from inverse lithography, which makes the pattern cells in the same groups identical to avoid a repeated verification and to improve the yield. The method comprises the step of: analyzing a target designed layout by hierarchy; categorizing the pattern cells with the same shape into a group; inversing the target designed layout by inverse lithography; inspecting the inversed pattern cells in the group with each other and replacing the variant ones to make all the inversed pattern cells identical.

REFERENCES:
patent: 5497334 (1996-03-01), Russell et al.
patent: 5528508 (1996-06-01), Russell et al.
patent: 2004/0031006 (2004-02-01), Kamon
patent: 2005/0125763 (2005-06-01), Lin et al.
patent: 2005/0268270 (2005-12-01), Kamon
patent: 2007/0124718 (2007-05-01), Kobayashi et al.
patent: 2007/0156379 (2007-07-01), Kulkarni et al.

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