Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2011-01-25
2011-01-25
Pizarro, Marcos D (Department: 2814)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C257S777000, C257SE21499, C257SE21530, C438S015000
Reexamination Certificate
active
07875499
ABSTRACT:
There are provided a plurality of semiconductor apparatuses judged as good items in electrical and functional inspections while having internal connection terminals disposed on electrode pads of semiconductor chips, resin layers which are disposed on surfaces of the semiconductor chips in which the electrode pads are formed and expose the internal connection terminals, and wiring patterns which are disposed on the resin layers and are connected to the internal connection terminals, a wiring substrate on which the plurality of semiconductor apparatuses are stepwise stacked, the wiring substrate electrically connected to the plurality of semiconductor apparatuses, and a sealing resin with which the plurality of semiconductor apparatuses are sealed.
REFERENCES:
patent: 2004/0104473 (2004-06-01), Farnworth
patent: 2004/0191955 (2004-09-01), Joshi et al.
patent: 2005/0017326 (2005-01-01), Iijima et al.
patent: 2005/0093167 (2005-05-01), Saeki
patent: 2005/0104228 (2005-05-01), Rigg et al.
patent: 2005/0212109 (2005-09-01), Cherukuri et al.
patent: 2006/0091518 (2006-05-01), Grafe et al.
patent: 2006/0223231 (2006-10-01), Koiwa et al.
patent: 1 032 041 (2000-08-01), None
patent: 2001-127256 (2001-05-01), None
patent: 2001-298150 (2001-10-01), None
patent: 2005-302871 (2005-10-01), None
patent: 2007-005800 (2007-01-01), None
patent: WO 2004/049436 (2004-06-01), None
patent: WO 2004049436 (2004-06-01), None
patent: WO 2006/037056 (2006-04-01), None
Drinker Biddle & Reath LLP
Gupta Raj
Pizarro Marcos D
Shinko Electric Industries Co. Ltd.
LandOfFree
Method of manufacturing a stacked semiconductor apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a stacked semiconductor apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a stacked semiconductor apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2669935