Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2011-08-09
2011-08-09
Lee, Hsien-ming (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S156000, C438S212000, C257S302000, C257S329000, C257SE21422
Reexamination Certificate
active
07993988
ABSTRACT:
Methods for fabricating a non-planar transistor. Fin field effect transistors (finFETs) are often built around a fin (e.g., a tall, thin semiconductive member). During manufacturing, a fin may encounter various mechanical stresses, e.g., inertial forces during movement of the substrate and fluid forces during cleaning steps. If the forces on the fin are too large, the fin may fracture and possibly render a transistor inoperative. Supporting one side of a fin before forming the second side of a fin creates stability in the fin structure, thereby counteracting many of the mechanical stresses incurred during manufacturing.
REFERENCES:
patent: 6090685 (2000-07-01), Gonzales et al.
patent: 6635909 (2003-10-01), Clark et al.
patent: 6767793 (2004-07-01), Clark et al.
patent: 7767100 (2010-08-01), Fehlhaber et al.
patent: 2005/0077553 (2005-04-01), Kim et al.
patent: 2005/0093067 (2005-05-01), Yeo et al.
patent: 2007/0076477 (2007-04-01), Hwang et al.
patent: 2004038770 (2004-05-01), None
T. Park, et al.: “Fabrication of Body-Tied FinFETs (Oega MOSFETs) Using Bulk Si Wafers”; 2003 Symposium on VLSI Technology Digest of Technical Papers; Jun. 2003, 2 pages.
R. Katsumata, et al.; “Fin-Array-FET on bulk silicon for sub-100 nm Trench Capacitor DRAM”; 2003 Symposium on VLSI Technology Digest of Technical Papers; Jun. 2003, 2 pages.
Fletcher Yoder
Lee Hsien-Ming
Micro)n Technology, Inc.
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