Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2011-03-08
2011-03-08
Choe, Yong (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S101000, C711S131000, C711S154000
Reexamination Certificate
active
07904667
ABSTRACT:
A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device. Each bit of the ODR can manipulate the state of a connected external binary device or can be read without changing the state. The memory device may include settable controlling bits and a set of controlled register bits. Setting the one or more controlling bits may define which controlled register bits are associated with the IRR and which are associated with the ODR.
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Beane Bill
Springer Casey
Wang Yunsheng
Wong Tak Kwong
Choe Yong
Hayes Boone LLP
Integrated Device Technology Inc.
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