Filtered register architecture to generate actuator signals

Details Filtered register architecture to generate actuator signals Filtered register architecture to generate actuator signals

2011-04-26

2011-04-26

Ellis, Kevin L (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

C711S103000

Reexamination Certificate

active

07934048

ABSTRACT:
In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced register including a first memory device including an first enable input, a first data input coupled to a register data input, and first memory device output, the first memory device output to couple to the memory array, and the enhances register to include a second memory device including a second enable input, a second data input coupled to the register data input, and a second memory device output, wherein the second memory device output provides a first output signal indicating when one or more of the actuator signals from the first memory device output are to be coupled to the register data input.

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“U.S. Appl. No. 11/642,038 Response to Restriction Requirement”, 6 pgs.
“U.S. Appl. No. 11/642,038 Restriction Requirement Received”, 4 pgs.
“U.S. Appl. No. 11/642,038, Notice of Allowance mailed Jul. 8, 2009”, 8 pgs.

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