Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2011-05-17
2011-05-17
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07945867
ABSTRACT:
A method for realizes electric connections in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components. The method includes: providing a nanometric circuit architecture comprising a succession of conductive nanowires substantially parallel to each other and extended along a direction x; realizing, above the succession, an insulating layer; opening, in the insulating layer, a window of nanometric width b extended along a direction inclined by an angle α with respect to the direction x to substantially cross the whole succession of nanowires, with exposure of a succession of exposed portions of the nanowires, one for each nanowire; realizing, above the insulating layer, a plurality of conductive dies extended along a direction y substantially orthogonal to the direction x and addressed towards the standard electronic components, each of such dies overlapping said window onto a respective exposed portion of a nanowire with obtainment of a plurality of contacts realizing said electric connections.
REFERENCES:
patent: 6128214 (2000-10-01), Kuekes et al.
patent: 6256767 (2001-07-01), Kuekes et al.
patent: 6458621 (2002-10-01), Beck
patent: 6699779 (2004-03-01), Chen et al.
patent: 7605066 (2009-10-01), Cerofolini et al.
patent: 2003/0108728 (2003-06-01), Heath et al.
patent: 2003/0203585 (2003-10-01), Hsu
patent: 2004/0181630 (2004-09-01), Jaiprakash et al.
patent: 1341184 (2003-09-01), None
patent: 1465201 (2004-10-01), None
patent: 20051029498 (2005-03-01), None
Austin, M., et al., “6 nm Half-Pitch Lines and 0.04 μm2Static Random Access Memory Patterns by Nanoimprint Lithography,”Nanotech., 16:1058-1061, May 2005.
Cerefolini, G., et al., “A Hybrid Approach to Nanoelectronics,”Nanotech., 16:1040-1047, May 2005.
DeHon, A., et al., “Stochastic Assembly of Sublithographic Nanoscale Interfaces,”IEEE Trans. Of Nanotech., 2 (3):165-174, Sep. 2003.
Melosh, N., et al., “Ultrahigh-Density Nanowire Lattices and Circuits,”Science, 300:112-115, Apr. 2003.
Cerofolini Gianfranco
Mascolo Danilo
Bowers Brandon W
Chiang Jack
Jorgenson Lisa K.
Satagaj Thomas J.
Seed IP Law Group PLLC
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