Semiconductor device and layout method thereof

Details Semiconductor device and layout method thereof Semiconductor device and layout method thereof

2011-03-22

2011-03-22

Richards, N Drew (Department: 2895)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

C257S202000, C257S210000, C257S296000, C257S690000, C257S693000, C257S734000

Reexamination Certificate

active

07911069

ABSTRACT:
A semiconductor device and a layout method thereof are provided, each of which contributes to a reduction in layout area and appropriately adjusts an inter-wiring capacitance even where wiring widths and intervals in a plurality of wiring layers differ at a bus wiring comprised of the wiring layers. In the semiconductor device, a first functional block and a second functional block are connected to each other, and a plurality of wirings formed over their corresponding wiring layers are provided. The wiring layers have constant wiring widths and wiring intervals for every wiring layer. The number of wirings on each wiring layer is determined, at least in part, by multiplying (a) the total number of required wirings (for all wiring layers) by (b) a ratio of (i) a rate of wirings per unit length on the given layer versus (ii) the sum of the rates of wirings per unit length for each of the plurality of wiring layers. Where the rate of wirings per unit length on a given layer is an inverse of the sum of (x) the desired or predetermined constant wiring width for that layer and (y) the desired or predetermined constant wiring interval for that layer.

REFERENCES:
patent: 2002/0064908 (2002-05-01), Awaya
patent: 11-233637 (1999-08-01), None
patent: 2009-87974 (2009-04-01), None

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