Semiconductor memory device and semiconductor memory system

Static information storage and retrieval – Read/write circuit – Common read and write circuit

Reexamination Certificate

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C365S189070, C365S233100

Reexamination Certificate

active

07876626

ABSTRACT:
A semiconductor memory device comprises a memory cell array including a plurality of memory cells arranged at intersections of word lines and bit lines; a read/write circuit operative to execute data read/write to the memory cell; and an operational circuit operative to compare certain length data read out by the read/write circuit from plural ones of the memory cells with certain length data to be written in the plural memory cells to make a decision, and create a flag representing the decision result. The read/write circuit inverts each bit in the certain length data to be written in the memory cells in accordance with the flag, and writes only rewrite-intended data of the certain length data and the flag. The read/write circuit reads the certain length data together with the flag corresponding thereto, and inverts each bit in the certain length data in accordance with the flag.

REFERENCES:
patent: 6111807 (2000-08-01), Ooishi
patent: 6259647 (2001-07-01), Ooishi
patent: 6396768 (2002-05-01), Ooishi
patent: 7106621 (2006-09-01), Frey
patent: 7518922 (2009-04-01), Maejima et al.
patent: 2007/0280031 (2007-12-01), Maejima et al.
patent: 7-240098 (1995-09-01), None
patent: 2005-108304 (2005-04-01), None
patent: 2005-157781 (2005-06-01), None

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