Reducing implant degradation in tilted implantations by...

Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region

Reexamination Certificate

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C438S531000, C438S942000, C438S944000

Reexamination Certificate

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07977225

ABSTRACT:
In extremely scaled semiconductor devices, an asymmetric transistor configuration may be established on the basis of tilted implantation processes with increased resist height and/or tilt angles during tilted implantation processes by providing an asymmetric mask arrangement for masked transistor elements. For this purpose, the implantation mask may be shifted by an appropriate amount so as to enhance the overall blocking effect for the masked transistors while reducing any shadowing effect of the implantation masks for the non-masked transistors. The shift of the implantation masks may be accomplished by performing the automatic alignment procedure on the basis of “shifted” target values or by providing asymmetrically arranged photolithography masks.

REFERENCES:
patent: 6008094 (1999-12-01), Krivokapic et al.
patent: 6187643 (2001-02-01), Borland
patent: 102006037751 (2008-02-01), None
Translation of Official Communication from German Patent Office for German Patent Application No. 10 2008 030 855.2-33 dated Apr. 9, 2009.

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