Semiconductor memory device and manufacturing method thereof

Details Semiconductor memory device and manufacturing method thereof Semiconductor memory device and manufacturing method thereof

Filed on

2011-07-12

Date issued

2011-07-12

Examiner

Ngo, Ngan (Department: 2893)

Patent Class

Active solid-state devices (e.g., transistors, solid-state diode

SubClass

Field effect device

SubSubClass

Having insulated electrode

Other Related Categories

C257S378000, C257S390000, C257SE29118

Type

Reexamination Certificate

Status

active

Patent number

07977738

Description

ABSTRACT:
A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.

REFERENCES:
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patent: 6621725 (2003-09-01), Ohsawa
patent: 6825524 (2004-11-01), Ikehashi et al.
patent: 2009/0179262 (2009-07-01), Holz et al.
patent: 2009/0315090 (2009-12-01), Weis et al.
patent: 2010/0061145 (2010-03-01), Weis
patent: 2003-68877 (2003-03-01), None
patent: 2005-79314 (2005-03-01), None
K. Okano, et al., “Process Integration Technology and Device Characteristics of CMOS FinFET on Bulk Silicon Substrate with sub-10 nm Fin Width and 20 nm Gate Length”, 2005 IEEE International Electron Devices Meeting Technical Digest, Dec. 5-7, 2005, 6 pages.

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