Methods for coordinating access to memory from at least two...

Electrical computers and digital processing systems: support – Multiple computer communication using cryptography – Particular communication authentication technique

Reexamination Certificate

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Details

C713S189000, C713S193000, C711S150000, C711S153000, C711S147000, C709S213000, C709S215000, C380S277000

Reexamination Certificate

active

07873830

ABSTRACT:
Electronic circuit chips which include cryptography functions are arranged in multichip configurations through the utilization of a shared external memory. Security of the chips is preserved via a handshaking protocol which permits each chip to access limited portions of the memory as defined in a way that preserves the same high security level as the tamper proof chips themselves. The chips may be operated to work on different tasks or to work on the same task thus providing a mechanism for trading off speed versus redundancy where desired.

REFERENCES:
patent: 5321752 (1994-06-01), Iwamura et al.
patent: 5513133 (1996-04-01), Cressel et al.
patent: 5764554 (1998-06-01), Monier
patent: 5825878 (1998-10-01), Takahashi et al.
patent: 6108524 (2000-08-01), Hershey et al.
patent: 6360303 (2002-03-01), Wisler et al.
patent: 6434699 (2002-08-01), Jones et al.
patent: 6625631 (2003-09-01), Ruehle
patent: 6789256 (2004-09-01), Kechriotis et al.
patent: 6804696 (2004-10-01), Chen et al.
patent: 2003/0133574 (2003-07-01), Caronni et al.
patent: 2004/0019771 (2004-01-01), Quach
patent: 2006/0107032 (2006-05-01), Paaske et al.
patent: 2006/0230439 (2006-10-01), Smith et al.
Suh et al. “AEGIS: A single-chip secure processor” Information Security Technical Report, 2005.
Shi, Weidong et al. “Architectural Support for High Speed Protection of Memory Integrity and Confidentiality in Multiprocessor Systems”, Proceedings of the 13th International Conference on Parallel Architecture and Compilation Techniques (PACT'04), 2004.
“A Circuit Chip for Cryptographic Processing Having a Secure Interface to an External Memory,” U.S. Appl. No. 10/938,835, filed Sep. 10, 2004.
Kornerup, Peter, “A Systolic, Linear-Array Muliplier for a Class of Right-Shift Algorithms,” IEEE Transactions on Computers, vol. 43, No. 8, pp. 892-898 (Aug. 1994).
Montgomery, Peter, “Modular Multiplication Without Trial Division,” Mathematics of Computation, vol. 44, No. 170, pp. 519-521 (Apr. 1985).

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