Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2011-01-18
2011-01-18
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07873929
ABSTRACT:
Method and apparatus for designing an integrated circuit. A new layout is generated for at least one standard cell that incorporates an auxiliary pattern on a gate layer to facilitate cell-based optical proximity correction. An original placement solution is modified for a plurality of standard cells to permit incorporation of cells containing auxiliary patterns while improving an objective function of a resulting placement solution for the plurality of standard cells.
REFERENCES:
patent: 2002/0003270 (2002-01-01), Makino
patent: 2007/0168898 (2007-07-01), Gupta et al.
Cao, K., Dobre, S., Hu, J., “Standard Cell Characterization Considering Lithography Induced Variations.” Proc. Of ACM/IEEE Design Automation Conferece, pp. 801-804 (2006).
Gupta, P., Heng, F., Lavin, M., “Merits of Cellwise Model-Based OPC.” Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing. vol. 5379, pp. 182-189 (2004).
Gupta, P., Kahng, A., Park, C., “Detailed Placement for Improved Depth of Focus and CD Control.” Proc. Asia and South Pacific Design Automation Conf., pp. 343-348 (Jan. 2005).
Gupta, P., Kahn, A., Nakagawa, S., Shah, S., Sharma, P., “Lithography Simulation-Based Full-Chip Design Analyses.” Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, pp. 61560T (2006).
Heng, F., Lee, J., Gupta, P., “Toward Through-Process Layout Quality Metrics.” Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing. pp. 161-167 (May 2005).
Kahng, A., Muddu, S., and Park, C., “Auxiliary Pattern-Based Optical Proximity Correction for Better Printability, Timing and Leakage Control.” J. Micro/Nanolith. MEMS MOEMS, vol. 7, 013002 (2008).
Matsunawa, T., Nosato, H., Sakanashi, H., Murakawa, M., Murata, N., Terasawa, T., Tanaka, T., Yoshioka, N., Suga, O., Higuchi, T., “The Novel Approach for Optical Proximity Correction Using Genetic Algorithms.” Proc. BACUS Symposium on Photomask Technology, 5992, pp. 54-1-54-9 (2005).
Wang, X., Pilloff, M., Tang, H. and Wu, C., “Exploiting Hierarchical Structure to Enhance cell-based RET with Localized OPC Reconfiguration.” Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, 5756, pp. 361-367 (2005).
Kahng Andrew B.
Park Chul-Hong
Greer Burns & Crain Ltd.
Siek Vuthe
The Regents of the University of California
LandOfFree
Method, apparatus and system for designing an integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method, apparatus and system for designing an integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method, apparatus and system for designing an integrated... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2653227