Integrated circuit tolerant to the locking phenomenon

Details Integrated circuit tolerant to the locking phenomenon Integrated circuit tolerant to the locking phenomenon

2011-01-11

2011-01-11

Fahmy, Wael M (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE27046, C257SE27063, C438S223000

Reexamination Certificate

active

07868392

ABSTRACT:
Integrated circuit comprising doped zones (3to8) formed in a substrate (1, 2), forming a parasitic thyristor structure with two parasitic bipolar transistors (T1, T2), the integrated circuit comprising two metallizations (16, 19) interconnecting each of the two corresponding doped zones (4, 5; 6, 7) of the integrated circuit, to reduce the base resistances (RP−, RP−) of the two bipolar transistors, at least one of the metallizations (16, 19) performed to reduce the base resistances (RN−, RP−) of the two bipolar transistors, being connected to a power supply metallization (15, 16) in the integrated circuit, entirely through the substrate (1, 2).

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patent: 60111454 (1985-06-01), None
French Preliminary Search Report dated Apr. 22, 2005 for French Application No. 04 07309.

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