EEPROM memory device and method of programming memory cell...

Details EEPROM memory device and method of programming memory cell... EEPROM memory device and method of programming memory cell...

2011-01-11

2011-01-11

Nguyen, Dao H (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185190, C365S185260, C365S185290, C365S185300, C257S296000, C257S315000, C257S316000, C257S390000, C257S681000, C257SE21680, C257SE21684, C257SE21690, C257SE21687, C257SE27103

Reexamination Certificate

active

07869279

ABSTRACT:
A memory device including a plurality of memory cells, each with access and program PMOS transistors situated in a common N-Well formed in a P-substrate, and an n-erase pocket formed directly in the P-substrate. Each cell includes a program PMOS including gate, and first and second P+ regions formed in an N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. Each cell further comprises an access PMOS including a gate, and first and second P+ regions formed within the same n-doped well as the first and second P+ regions of the program PMOS, wherein the first P+ region is electrically connected to the second P+ region of the program PMOS, and the gate is electrically connected to a corresponding word line. Each cell further includes an n-doped erase pocket including gate, and first and second N+ regions electrically connected to a corresponding erase line, and the gate is electrically connected to the gate of the program PMOS, forming the floating gate of the cell. The program and access PMOS of cells common to a bit line may be formed in a continuous N-Well. The first and second N+ regions of the n-doped erase pocket can be shorted by a substantially uniformly doped diffusion region.

REFERENCES:
patent: 7436710 (2008-10-01), Ratnakumar et al.
patent: 2008/0273392 (2008-11-01), Ratnakumar et al.

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