Simultaneous speculative threading light mode

Details Simultaneous speculative threading light mode Simultaneous speculative threading light mode

2011-08-23

2011-08-23

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Reexamination Certificate

active

08006073

ABSTRACT:
A system and method for management of resource allocation of threads for efficient execution of instructions. Prior to dispatching decoded instructions of a first thread from the instruction fetch unit to a buffer within a scheduler, logic within the instruction fetch unit may determine the buffer is already full of dispatched instructions. However, the logic may also determine that a buffer for a second thread within the core or micro core is available. The second buffer may receive and issue decoded instructions for the first thread until the buffer is becomes unavailable. While the second buffer receives and issues instructions for the first thread, the throughput of the system for the first thread may increase due to a reduction in wait cycles.

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U.S. Appl. No. 61/052,536, filed May 12, 2008.

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