Self-aligned metal-semiconductor alloy and metallization for...

Details Self-aligned metal-semiconductor alloy and metallization for... Self-aligned metal-semiconductor alloy and metallization for...

2011-02-15

2011-02-15

Garber, Charles D (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE27060

Reexamination Certificate

active

07888742

ABSTRACT:
A lateral double-gate FET structure with sub-lithographic source and drain regions is disclosed. The sub-lithographic source and drain regions are defined by a sacrificial spacer. Self-aligned metal-semiconductor alloy and metal contacts are made to the sub-lithographic source and drain using conventional silicon processing.

REFERENCES:
patent: 5773331 (1998-06-01), Solomon et al.
patent: 6580132 (2003-06-01), Chan et al.
patent: 6642115 (2003-11-01), Cohen et al.
patent: 2005/0263797 (2005-12-01), Chan et al.
patent: 2006/0284249 (2006-12-01), Chen et al.

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