Current steering digital-to-analog converter

Details Current steering digital-to-analog converter Current steering digital-to-analog converter

2011-08-09

2011-08-09

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S155000

Reexamination Certificate

active

07994957

ABSTRACT:
A digital to analog converter (DAC) module receives an input digital signal having a first data rate and is associated with a first frequency, the DAC module also receiving a synchronization signal having a second frequency that is higher than the first frequency. The DAC module includes an up-sampling circuit to generate a first digital signal having bit values of the input digital signal alternating with zero values, the first digital signal having a data rate that is higher than the first data rate; a delay circuit to delay the first digital signal by a time period to generate a second digital signal; a first DAC cell to generate a first analog signal based on the first digital signal, the first DAC cell being synchronized by the synchronization signal; a second DAC cell to generate a second analog signal based on the second digital signal, the second DAC cell being synchronized by the synchronization signal; and an adder to sum the first and second analog signals and generate a third analog signal.

REFERENCES:
patent: 4972188 (1990-11-01), Clement et al.
patent: 5880689 (1999-03-01), Kushner
patent: 6061010 (2000-05-01), Adams et al.
patent: 6466143 (2002-10-01), Eshraghi et al.
patent: 6977602 (2005-12-01), Ostrem et al.
patent: 7193547 (2007-03-01), Ho et al.
patent: 7206359 (2007-04-01), Kjeldsen et al.
patent: 7221298 (2007-05-01), Persons
patent: 7224304 (2007-05-01), Schoner
patent: 7777658 (2010-08-01), Nguyen et al.
patent: 2006/0139193 (2006-06-01), Morrow et al.
patent: 1 453 206 (2004-01-01), None
Clara et al., “A 350MHz Low-OSR ΔΣ Current—Steering DAC With Active Termination in 0.13 μm CMOS”, ISSCC 2005/Session 6/High-Speed and Oversampled DACs/6.5, 2005 IEEE International Solid-State Circuits Conference, Feb. 2005, pp. 118-119, 588.
Nguyen et al., “A 108 dB SNR, 1.1 mW Oversampling Audio DAC With A Three-level DEM Technique”, IEEE Journal of Solid-State Circuits, vol. 43, No. 12, Dec. 2008, pp. 2592-2600.
Nguyen et al., “A 113dB SNR Oversampling Sigma-Delta DAC for CD/DVD Application”, IEEE 1998, vol. 44, No. 3, Aug. 1998, pp. 1019-1023.
Van Tuijl et al., “A 128f, Multi-Bit ΣΔ CMOS Audio DAC With Real-Time DEM and 115dB SFDR”, ISSCC 2004/Session 20/Digital-To-Analog Converters/20.5, IEEE International Solid-State Circuits Conference, Feb. 18, 2004, 8 pages.
Adams et al., “A 113dB SNR Oversampling DAC With Segmented Noise-Shaped Scrambling”, ISSCC98/Session 4/Oversampling Converters/Paper TP 4.3, 1998 IEEE International Solid-State Circuits Conference, Digest of Digital Papers, Feb. 5, 1998, pp. 62-63, 413.
Nguyen et al., “A 113dB SNR Oversampling Sigma-Delta DAC for CD/DVD Application”, THPM 24.3, IEEE, Mar. 1998, pp. 404-405.
Nguyen et al., “A 108dB SNR 1.1mW Oversampling Audio DAC With A Three-level DEM Technique”, ISSCC 2008/Session 27/ΔΣ Data Converters/27.1, IEEE International Solid-State Circuits Conference, Feb. 6, 2008, Digest of Digital Papers, pp. 488-489, 630.
PCT Search Report, PCT Application No. PCT/EP2010/058175, dated Oct. 14, 2010.

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