High speed multiple memory interface I/O cell

Details High speed multiple memory interface I/O cell High speed multiple memory interface I/O cell

2011-01-25

2011-01-25

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S035000, C326S086000, C326S087000

Reexamination Certificate

active

07876123

ABSTRACT:
An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.

REFERENCES:
patent: 5481207 (1996-01-01), Crafts
patent: 6636069 (2003-10-01), Muljono
patent: 2005/0117433 (2005-06-01), Fujisawa
patent: 2006/0091900 (2006-05-01), Kang et al.

Affiliated with

Also associated with

Rating

High speed multiple memory interface I/O cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed multiple memory interface I/O cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed multiple memory interface I/O cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2641314