Postamble timing for DDR memories

Details Postamble timing for DDR memories Postamble timing for DDR memories

2011-01-25

2011-01-25

Barnie, Rexford N (Department: 2819)

Static information storage and retrieval

Read/write circuit

Signals

C326S093000, C327S170000, C327S172000

Reexamination Certificate

active

07876630

ABSTRACT:
Circuits, methods, and apparatus that isolate an input register from spurious transitions on a DQS signal. One example receives an enable signal from a core. A logic circuit, which may be referred to as a one-half period circuit, shortens enable pulses at their front end by one-half a period. The shortened enable signal is passed to a storage element such as a register. Active pulses of the shortened enable signal clear the register, which provides a control signal closing a switch, such as an AND gate. The switch passes the DQS signal to the input register when closed and isolates the input register from the DQS signal when open. The shortened enable signal prevents the switch from opening early and passing spurious transitions on the DQS signal, for example during back-to-back non-consecutive read cycles.

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patent: 2003/0147299 (2003-08-01), Setogawa
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