Method and apparatus for implementing carry chains on field...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07873934

ABSTRACT:
A method for designing a system to be implemented on a field programmable gate array (FPGA) includes identifying an adder from an intermediate representation of the system. Components on the target device are designated to support and implement the adder as a partitioned adder having a plurality of sub-adders each registering an intermediate result.

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Juang et al.; “Partition methodology for the final adder in a tree-structure parallel multiplier generator”; Publication Year: 2002; Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on; vol. 1; pp. 471-474 vol. 1.
Li et al.; “A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability”; Publication Year: 2005; Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on; pp. 77-80 vol. 1.

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