Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2011-02-22
2011-02-22
Weiss, Howard (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
07893501
ABSTRACT:
A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.
REFERENCES:
patent: 5023676 (1991-06-01), Tatsuta
patent: 6437404 (2002-08-01), Xiang et al.
patent: 6573172 (2003-06-01), En et al.
patent: 6870230 (2005-03-01), Matsuda et al.
patent: 6977194 (2005-12-01), Belyansky et al.
patent: 6982465 (2006-01-01), Kumagai et al.
patent: 7022561 (2006-04-01), Huang et al.
patent: 7205615 (2007-04-01), Tsutsui et al.
patent: 7417289 (2008-08-01), Tsutsui et al.
patent: 2003/0040158 (2003-02-01), Saitoh
patent: 2004/0075148 (2004-04-01), Kumagai et al.
patent: 2005/0194596 (2005-09-01), Chan et al.
patent: 52-120776 (1977-10-01), None
patent: 60-236209 (1985-11-01), None
patent: 01-042840 (1989-02-01), None
patent: 2003-086708 (2003-03-01), None
patent: 2004-193166 (2004-07-01), None
Shimizu, A., et al., “Local Mechanical-Stress Comtrol (LMC): A New Technique for CMOS—Performance Enhancement”, 2001, IEDM 01, p. 19.4.1-19.4.4.
Japanese Office Action, with English translation, issued in Japanese Patent Application No. 2003-170335, mailed Dec. 22, 2009.
Japanese Office Action, with English translation, issued in Japanese Patent Application No. 2003-170335, mailed Mar. 23, 2010.
Akamatsu Kaori
Tsutsui Masafumi
Umimoto Hiroyuki
McDermott Will & Emery LLP
Panasonic Corporation
Weiss Howard
LandOfFree
Semiconductor device including MISFET having internal stress... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device including MISFET having internal stress..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device including MISFET having internal stress... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2636180