Semiconductor memory device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S247000

Reexamination Certificate

active

07910975

ABSTRACT:
The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line.

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Chinese Office Action, with English translation thereof, issued in Patent Application No. 2005800183321 dated on Aug. 1, 2008.
Kuo, C., et al. “A Capacitorless Double Gate DRAM Technology for Sub-100-nm Embedded and Stand-Alone Memory Applications” IEEE Transactions of Electron Devices, Dec. 2003, vol. 50, No. 12, pp. 2408-2416.
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Ohsawa, T., et al. “Memory Design Using One-Transistor Gain Cell on SOI” Digest of Technical Papers, IEEE International Solid-State Circuits Conference, Feb. 5, 2002, pp. 152-153, 454-455.

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