Multi-sample read circuit having test mode of operation

Details Multi-sample read circuit having test mode of operation Multi-sample read circuit having test mode of operation

2011-03-22

2011-03-22

Britt, Cynthia (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

07913130

ABSTRACT:
A data storage device includes non-volatile memory; and a read circuit for performing multi-sample read operations on the memory during a normal mode of operation. The read circuit includes a digital counter having an output that indicates a single bit (e.g., a sign-bit). The read circuit allows an external device (e.g., a memory tester) to supply test clock pulses to an input of the digital counter during a test mode. The test clock pulses can be counted to determine a state of the digital counter.

REFERENCES:
patent: 6188615 (2001-02-01), Perner et al.
patent: 6529460 (2003-03-01), Belser
patent: 7009901 (2006-03-01), Baker
patent: 410027498 (1998-01-01), None
patent: 2002056810 (2002-03-01), None

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