Memory controller and method for optimized read/modify/write...

Details Memory controller and method for optimized read/modify/write... Memory controller and method for optimized read/modify/write...

2011-03-15

2011-03-15

Ellis, Kevin L (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S170000, C714S702000

Reexamination Certificate

active

07908443

ABSTRACT:
A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.

REFERENCES:
patent: 5987628 (1999-11-01), Von Bokern et al.
patent: 6490462 (2002-12-01), Ozulturk et al.
patent: 6490642 (2002-12-01), Thekkath et al.
patent: 6718444 (2004-04-01), Hughes
patent: 6973551 (2005-12-01), Walton

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