Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2011-02-01
2011-02-01
Choe, Yong (Department: 2185)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S117000, C711S154000, C711S170000, C719S324000
Reexamination Certificate
active
07882329
ABSTRACT:
Provided are techniques for cancellation of premigration of a member in a chain. A set of premigration messages are received, wherein a separate premigration message is received for each logical volume in a chain of logical volumes. While processing the premigration messages in order of receipt of each of the premigration messages, a cancel message indicating that premigration of a logical volume in the chain is to be cancelled is received. In response to determining that the logical volume whose premigration is to be cancelled has not already been transferred to physical storage media, premigration of the logical volume is cancelled by removing a premigration message for that logical volume from the set of premigration messages and premigration of each other logical volume in the chain of logical volumes is continued in order of receipt.
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US Patent application entitled “Cancellation of Individual Logical Volumes in Premigration Chains”, Serial No. unknown, filed Sep. 24, 2007, by inventors C.M. Friauf, N. Iwasaki, Y. Kibuse, G.T. Kishi and K. Masuda.
Friauf Cheryl Marie
Iwasaki Norie
Kibuse Yuuji
Kishi Gregory Tad
Masuda Koichi
Choe Yong
Davda Janaki K.
International Business Machines - Corporation
Konrad Raynes & Victor LLP
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