Multi-level memory cell utilizing measurement time delay as...

Details Multi-level memory cell utilizing measurement time delay as... Multi-level memory cell utilizing measurement time delay as...

2011-02-22

2011-02-22

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S148000

Reexamination Certificate

active

07894272

ABSTRACT:
A computer program product for operating a memory cell and memory array. The computer program product of memory cell operation entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time.

REFERENCES:
patent: 7532498 (2009-05-01), Chow et al.
patent: 7764532 (2010-07-01), Kurjanowicz et al.
patent: 2007/0091664 (2007-04-01), Chow et al.

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