Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2011-07-26

2011-07-26

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S203000, C365S230060

Reexamination Certificate

active

07986547

ABSTRACT:
A semiconductor memory device includes a memory cell array having a plurality of read word lines, a plurality of first and second read bit lines, and a plurality of memory cells arranged in array. The memory cell includes a first and a second cell node in complementary pair, a first drive transistor controlled by the second cell node, and a second drive transistor controlled by the first cell node. The read word line and the first read bit line are connected with each other via the first drive transistor. The read word line and the second read bit line are connected with each other via the second drive transistor.

REFERENCES:
patent: 7440313 (2008-10-01), Abeln et al.
patent: 7630272 (2009-12-01), Kenkare et al.
patent: 7684264 (2010-03-01), Hunter et al.
patent: 2007/0242513 (2007-10-01), Chang et al.
patent: 2008/0089145 (2008-04-01), Luthra
patent: 2008/0117707 (2008-05-01), Manickavasakam et al.
Leland Chang, et al., “Stable SRAM Cell Design for the 32 nm Node and Beyond”, 2005 Symposium on VLSI Technology Digest of Technical Papers, 2005, pp. 128-129.

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