Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-12-02
2001-11-06
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S382000, C257S627000
Reexamination Certificate
active
06313494
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device having a self-aligned contact pad.
2. Description Related Art
Generally, if the degree of the integration of a semiconductor device is increased by reducing design dimensions in the semiconductor device, tolerance for the alignment of a contact hole with respect to lower semiconductor layers and lower wiring can become increasingly difficult.
Heretofore, a method of forming a contact pad using a selective anisotropic epitaxial silicon growth technique to solve such a problem was known. The above forming method using the selective anisotropic epitaxial silicon growth technique is described, for example, by Hada et al, “A Self-Aligned Contact Technology Using Anisotropic Selective Epitaxial Silicon For Giga-Bit DRAMs,” IEDM Technical Digest, p.665, 1995.
FIG. 1
shows an arrangement wherein corners portions
2
of a diffusion layer
1
are exposed between word lines
3
. The shape of the diffusion layer
1
is rectangular. (Diffusion layer
1
is an element forming region having portions into which dopants are diffused.) Crystal orientations of the long sides and the short sides of the diffusion layer
1
are arranged <
110
>. In this case, silicon is selectively grown on a diffusion layer
18
. For example, the silicon is selectively subjected to anisotropic epitaxial growth using Si
2
H
6
gas and PH
3
gas, setting the flow rate of Si
2
H
6
gas to 1 cc per minute and setting the temperature of a silicon substrate to 700° C.
But if the corner portion
2
of the diffusion layer
1
is rounded, the crystal orientation of the corner portion
2
does not become <
110
>. As a result, ideal anisotropic growth may not occur and isotropic growth may occur.
FIG. 2
is a sectional view taken along the line II—II,
FIG. 2
shows that if the silicon epitaxial growth is isotropic growth, there is a problem that epitaxial silicon
8
laterally grown is grown on element separating regions
5
, and brought into contact with each other to cause a short circuit.
Moreover, as shown in
FIG. 3
, a crystal plane (facet) having crystal orientation other than [100] may be generated. If such facets are generated, as shown in
FIG. 3
, there is a problem that both upper parts of first facets
19
and second facets
20
are connected during growth to thereby block further vertical epitaxial growth.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device in which isotropic growth is avoided when silicon is selectively subjected to anisotropic epitaxial growth on source regions and drain regions of a memory cell transistor.
Another object of the present invention is to provide a semiconductor device in which no crystal plane having crystal orientation other than [100] is produced when silicon is selectively subjected to anisotropic epitaxial growth on the source regions and the drain regions of a memory cell transistor.
Another object of the present invention is to provide a semiconductor device covering rounded corners of the diffusion layer with a word line so as to grow source or drain contact pads preferably from the diffusion layer.
REFERENCES:
patent: 5231043 (1993-07-01), Chan et al.
patent: 5401681 (1995-03-01), Dennison
patent: 5753555 (1998-05-01), Hada
patent: 5895948 (1999-04-01), Mori et al.
patent: 6064084 (2000-05-01), Tanahashi
patent: 63-9964 (1988-01-01), None
patent: 3-72675 (1991-03-01), None
patent: 3-272169 (1991-12-01), None
patent: 6-5814 (1994-01-01), None
patent: 7-74164 (1995-03-01), None
patent: 10-154799 (1998-06-01), None
patent: 11-97648 (1999-04-01), None
Hada et al. “A Self-Aligned Contact Technology Using Anisotropical Selective Epitaxial Silicon For Giga-Bit DRAMs,” International Electron Devices Meeting, Washington D.C. Dec. 10-13, 1995, pp. 665-668.
H. Hada, et al., “A Self-Aligned Contact Technology Using Anisotropical Selective Epitaxial Silicon for Giga-Bit DRAMs,” pp. 665-668,IEEE.
Crane Sara
NEC Corporation
Young & Thompson
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