Memory arbitration scheme with circular sequence register

Details Memory arbitration scheme with circular sequence register Memory arbitration scheme with circular sequence register

1999-05-19

2001-11-20

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S151000, C711S152000, C710S040000, C710S111000, C710S244000

Reexamination Certificate

active

06321309

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method and apparatus for arbitrating between requests from various sources for access to a shared resource, particularly, although not exclusively, memory in a computer system.
Known arbitration schemes for memory access frequently operate on the basis of granting access to the first received request or according to a fixed priority scheme wherein a request from one source always has priority over a request from another source.
The primary problem with such schemes is that, when incorporated in an integrated circuit, they cannot thereafter be changed. Further, they are inflexible in the sense that they do not take account of whereas some sources may be accorded a high priority but only require a small amount of memory, other sources with another priority may have a need for a greater number of memory accesses, i.e. a greater memory “bandwidth”. It is an object of the present invention to overcome or at least reduce these problems.
SUMMARY OF THE INVENTION
The present invention provides apparatus for arbitrating between requests from a plurality of sources for access to a shared resource, the apparatus comprising:
a register means having a plurality of stages, each stage containing a designation of one of said sources, a plurality of stages containing a designation of the same source,
logic means for accessing the register stages according to a priority scheme and for comparing the designation in each stage with requests for access, and granting access according to the match between the highest priority source designation and a memory request, and means for changing the contents of the register means subsequent to access grant.
The register means comprises a sequence register or circulating register, which cyclically rotates the contents of the register through the stages, so that when a source designation reaches the last stage in the register, it is then rotated back to the first stage in the register.
Conveniently, the logic means will compare the contents of the register with the received memory requests; if one or more matches are achieved, access is granted to the stage with the highest priority. The register stage therefore represents the highest priority access, which changes dynamically as the register is rotated.
Thus, the advantage of such an arrangement is that the priority scheme can be selectively programmed. Furthermore, if a particular source has a large memory bandwidth requirement, then more register stages may contain a designation of this source as opposed to other sources; other sources may however have a higher priority at any given point in time. The priority scheme can be changed dynamically by changing the contents of the register.
In a further aspect, the present invention provides a method for arbitrating between requests from a plurality of sources for access to a shared resource, comprising:
providing a register means with a plurality of stages, and designating within each of said stages one of said sources, and designating in a plurality of stages the same source, and
accessing the stages according to a fixed priority scheme to compare the designation in the stage with requests for access from said sources, and granting access according to the designations within the register stages, and changing the contents of the registers subsequent to access grant.


REFERENCES:
patent: 4400771 (1983-08-01), Suzuki et al.
patent: 5303382 (1994-04-01), Buch et al.
patent: 6178486 (2001-01-01), Gill et al.
patent: 1377557 (1974-12-01), None

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