Process to separate the doping of polygate and source drain...

Details Process to separate the doping of polygate and source drain... Process to separate the doping of polygate and source drain...

1996-03-27

2001-11-20

Low, Christopher S. F. (Department: 1653)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S591000, C438S660000, C438S655000, C438S657000

Reexamination Certificate

active

06319804

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Use
The invention relates to field effect transistor formation, and particularly to doping of the source-drain regions and the gate of a field effect transistor.
2. Description of Related Art
One of the most common building blocks in conventional electronic technology is the MOSFET transistor. As shown in the cross-section of
FIG. 1
, a MOSFET transistor
10
is composed of a substrate
12
upon which is formed a conducting gate
13
, often formed of polysilicon. This gate is formed on top of a relatively thin insulating layer
19
, often formed of thermal oxide, which electrically isolates the gate
13
from the underlying substrate
12
. Within substrate
12
and on either side of polysilicon gate
13
are formed source and drain regions
14
and
15
(collectively, “source-drain regions”). MOSFET device
10
is separated from other devices which are formed on the same silicon wafer by isolation regions
16
, which are conventionally formed of an oxide grown on substrate
12
.
In forming a conventional MOSFET device
10
, isolation regions
16
are first grown or otherwise formed on substrate
12
. A thin oxide layer
19
is grown, and a polysilicon layer is then deposited over thin oxide layer
19
and subsequently etched to form polysilicon gate
13
. With polysilicon gate
13
acting as a natural mask, source-drain regions
14
and
15
are implanted with either an n-type or a p-type dopant (an n-type dopant is shown in
FIG. 1
a
). While source-drain regions
14
and
15
are being doped, polysilicon gate
13
is also simultaneously doped with the same type of dopant as is used for doping the source-drain regions. Source-drain regions
14
and
15
are subsequently activated by heating the structure, causing annealing to occur by exposing the wafer to approximately 1000° C.
Optionally, as shown in the cross-section of
FIG. 1
b,
some devices are formed to have lightly doped source and drain (LDD) regions
17
. To form LDD regions
17
, substrate
12
with polysilicon gate
13
is first implanted or otherwise exposed to a dopant (either n-type or p-type). Spacers
18
are formed abutting gate
13
. Substrate
12
with gate
13
and spacers
18
are then again exposed to the same type of dopant (n or p) as was previously used, to form more heavily doped source-drain regions
14
and
15
. Spacers
18
protect the underlying substrate regions from further doping, resulting in LDD regions
17
.
MOSFET transistors are subject to widespread use because of their high performance characteristics compared to other technologies as well as their relative ease of manufacturability. However, it is believed from simulation and experiment that another type of transistor, a FermiFET transistor, has even more desirable performance characteristics than a traditional MOSFET transistor, including higher drive currents, lower junction and/or gate capacitance, and better reliability.
A cross-section of a FermiFET transistor is shown in FIG.
2
. FermiFETs are structurally similar to the traditional MOSFET of
FIG. 1
, except that polysilicon gate
53
is oppositely doped from source-drain regions
54
and
55
. That is, if source-drain regions
54
and
55
are n-doped, gate
53
is p-doped. Likewise, if source-drain regions
54
and
55
are p-doped, gate
53
is n-doped. In addition, Fermitub
57
is positioned between source-drain regions and below the gate and is formed in the substrate region, doped with the same type of dopant as source-drain regions
54
and
55
.
While a FermiFET may possess improved performance characteristics, the opposite doping of gate and source-drain regions in a FermiFET creates the manufacturing dilemma of having to dope the gate oppositely from the source and drain, a dilemma which does not exist when forming the conventional MOSFET device of
FIG. 1
, in which both the source-drain and the gate regions are doped simultaneously. The doping of the source-drain regions is typically a heavy doping. Such heavy doping will also occur to the gate if left unmasked. Subsequent counter-doping of the gate to attain opposite net doping is difficult, particularly because mask alignment over or around the gate region to allow such counter-doping (or to prevent doping in the first place) is difficult once the gate has been cut. Subsequent counter-doping and mask alignment becomes increasingly troublesome when other devices such as conventional MOSFETs and other oppositely-doped FermiFETs are also being formed on a single wafer. Misalignment of the mask can lead to doping in inappropriate regions and create a non-working device.
Thus, while the benefits of FermiFETs have been simulated, they have gone virtually unused because of difficulties in fabricating multiple devices on a single wafer, and particularly in achieving an oppositely doped gate.
In addition, conventional MOSFET devices, such as those shown in
FIGS. 1
a
and
1
b,
often experience less than optimal performance when the source-drain regions and the gate are doped at equal levels with the same type of dopant. For instance, when the source-drain regions are heavily doped with boron, the gate will also be heavily doped with boron, which may lead to boron penetration. During high temperature processing steps, boron diffuses from the gate into the substrate, changing the characteristics of the substrate region and thin insulating layer underlying the gate. If the gate were to be lightly doped with boron or some other material, while the source-drain regions remained heavily doped with boron, boron penetration would be minimized. However, as with FermiFET formation, problems occur with subsequent counter-doping and mask placement in trying to form variant doping levels between the gate and the source-drain regions.
Given these problems, it is desirable to develop a method of independently doping the gate and the source-drain regions of a transistor device, and to do so in a way that requires no counter-doping or mask alignment over a formed gate.
One proposed method for achieving independent doping of the source-drain regions and the gate region is demonstrated with reference to
FIGS. 3-5
. In
FIG. 3
, a layer of polysilicon
113
is deposited over thin oxide region
119
and substrate
112
having field oxide regions
116
. Polysilicon region
113
is doped with a first dopant, which is a p-type dopant in FIG.
3
. An oxide blocking layer
120
is formed over polysilicon layer
113
. Oxide layer
120
and polysilicon layer
113
are etched to form gate stack
125
in FIG.
4
. Subsequently, source-drain regions
114
and
115
are implanted with a second dopant, which is an n-type dopant in FIG.
4
. During the implanting of regions
114
and
115
, polysilicon region
113
is protected from further doping by oxide layer
120
.
In order to form contacts with the source-drain regions
114
and
115
as well as the gate region
113
, titanium silicide (TiSi
2
) is conventionally grown upon these regions (source, drain and gate). TiSi
2
also lowers the device resistance and increases the device speed. However, in order to grow TiSi
2
on the polysilicon gate region
113
of
FIG. 4
, oxide layer
120
must be removed from gate stack
125
. The process of etching oxide layer
120
will also cause field oxide isolation regions
116
to be etched down as well. As a result and as shown in
FIG. 5
, when titanium silicide layer
130
is grown on source-drain regions
114
and
115
, junction leakage along the edges of source-drain regions
114
and
115
can occur. In an extreme case, the titanium silicide layer
130
will go below the n-doped regions
114
and
115
, causing a short to the substrate
112
. Both junction leakage and shorting cause unacceptable device characteristics, making this proposed method difficult to reliably utilize.
Thus, a more reliable method of independently doping the gate and source-drain regions of a transistor device in a manner that does not require removal of the blocking layer is desired.
SUMMARY OF THE INVENTION
The present invention, ro

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