Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-06-03
2001-02-06
Lintz, Paul R. (Department: 2768)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C703S014000, C703S013000
Reexamination Certificate
active
06185726
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to creating and implementing electronic circuits, and relates more particularly to a system and method for efficiently designing integrated circuit devices.
2. Description of the Background Art
Implementing an efficient and effective method for designing integrated circuits is a significant consideration of electronic component designers and manufacturers. The efficient design and testing of integrated circuits is often an extremely complex and time-consuming task due to the large number of electrical components and separate electrical circuits that typically comprise an integrated circuit. The complexity of the integrated circuit design procedure thus presents a substantial number of obstacles to successfully producing a final product that performs without operational errors.
Referring now to
FIG. 1
, a plan view of an exemplary floorplan for an integrated circuit
112
is shown, in accordance with the present invention. In the
FIG. 1
example, integrated circuit
112
includes a number of circuit blocks
114
-
118
, which are precisely positioned upon a surface of integrated circuit
112
according to a previously determined circuit design. Each of the circuit blocks
114
-
118
typically includes a substantial number of individual electrical components, including digital logic gates, which are selected to effectively perform the particular function for which integrated circuit
112
is designed.
According to modem practices, the procedure for designing and testing integrated circuit
112
may effectively be performed by integrated circuit designers who frequently use a special computer system to simulate the operation of a specific integrated circuit as the integrated circuit is being designed. The circuit designers may then advantageously test and modify the integrated circuit design to achieve optimal performance and reliability from the integrated circuit without actually re-fabricating the device after every design change or modification.
Due to the complex nature of integrated circuit design, successful techniques for decreasing design time without increasing design errors would likely result in more effective production of integrated circuits. The goals of reducing design time and reducing design errors must therefore be significant aspects of any effort to improve upon the currently existing integrated circuit design methodologies.
In some integrated circuit design procedures, the designing and testing are typically performed in serial fashion, with designers conducting the entire time-consuming design procedure to identify, correct and test a single design defect before any subsequent design defects may be addressed. The foregoing serial design procedure thus restricts the speed and efficiency of the integrated circuit design procedure, and results in an ineffective methodology for designing integrated circuits.
In other integrated circuit design procedures, designers have sometimes attempted to increase the speed and efficiency of the design procedure at the expense of permitting significant design errors to remain in the resultant integrated circuit designs. To compound this design error problem, the foregoing design procedures may fail to provide a coordinated checking system for managing design errors. The lack of a satisfactory design error checking system may result in design errors that are not detected, and also may create additional delays in the already lengthy integrated circuit design procedure.
SUMMARY OF THE INVENTION
An integrated circuit design procedure is required that permits circuit designers to effectively design and test new integrated circuit designs in a reduced amount of time by structuring the design procedure in an efficient manner. What is also required is an integrated circuit design procedure that advantageously provides an effective and organized methodology for checking integrated circuit parameters during the design procedure to facilitate rapid completion of the design procedure and thereby produce integrated circuits without design defects.
In accordance with the present invention, a system and method are disclosed for efficiently designing integrated circuit devices. The invention includes a computer system comprising a central processing unit (CPU) and a memory having a verification manager, a synthesis manager, and a backend manager.
In operation, an integrated circuit designer initially uses the verification manager to identify and correct a design defect that is present in an integrated circuit design that is currently being created and tested. The verification manager then generates new HDL (hardware description language) code corresponding to the entire integrated circuit design. The generated HDL code incorporates the design change necessitated by the foregoing design defect.
The verification manager then simulates and examines the operation of the integrated circuit design, especially in the circuitry of the previously-corrected design defect. Next, the verification manager performs a regression test and responsively determines whether the integrated circuit has passed the regression test. The regression test preferably analyzes the overall operation of the integrated circuit to ensure that the prior modification of the HDL code has not created additional design defects or related problems in other parts of the integrated circuit.
In addition to the regression test, the verification manager performs a checklist of selected regression checkpoints to eliminate any design errors, and to also facilitate the integrated circuit design procedure. If the integrated circuit fails to pass the regression test, then the verification manager selectively modifies the HDL code to correct for any problems detected by the failed regression test.
However, if the integrated circuit design passes the regression test, then a synthesis process begins. In one embodiment of the present invention, once the synthesis process begins, then a different designer may initiate another verification process to correct a new and separate design defect. Several designers may thus conduct multiple design processes concurrently to expedite the integrated circuit design procedure.
The synthesis manager next performs a synthesis procedure that preferably uses a synthesis program tool to convert the HDL code into specific electronic component specifications. Then, the synthesis manager performs a timing test and responsively determines whether the integrated circuit has passed the timing test. The timing test preferably analyzes the internal timing parameters of the integrated circuit to ensure that the circuit timing parameters fall within predetermined specifications for the particular integrated circuit design. In addition to the timing test, the synthesis manager performs a checklist of selected timing checkpoints, which eliminate any timing errors, and also facilitate the integrated circuit design procedure.
If the integrated circuit fails to pass the timing test, then, the synthesis manager modifies related constraint scripts to allow the integrated circuit to pass the timing test. However, if the integrated circuit design passes the timing test, then the synthesis manager generates a first net list which includes connectivity information specifying the entire integrated circuit design at the component level.
Then, a backend process begins to complete the final implementation of the integrated circuit design by specifying actual physical locations for the specific integrated circuit components. As discussed above, in many embodiments of the present invention, once the a verification, synthesis, or a backend process completes, then the designers may re-initiate those completed processes to continue refining a particular integrated circuit design. Several designers may thus conduct multiple design processes concurrently to expedite the integrated circuit design procedure in accordance with the present invention.
The backend manager then creates a floorplan, which include
Koerner Gregory J.
Lintz Paul R.
Simon & Koerner LLP
Sony Corporation
Thompson Annette M.
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