Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
Reexamination Certificate
1999-02-22
2001-11-20
Coulter, Kenneth R (Department: 2154)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error count or rate
C709S227000, C709S228000, C709S224000, C714S004110
Reexamination Certificate
active
06321350
ABSTRACT:
FIELD OF INVENTION
The subject of the present invention in general pertains to a new Input-Output facility design that exploits high bandwidth integrated network adapters.
BACKGROUND OF THE INVENTION
In a network computing environment, multitudes of commands and requests for retrieval and storage of data are processed every second. To properly address the complexity of routing these commands and requests, environments with servers have traditionally offered integrated network connectivity to allow direct attachments of clients such as Local Area Networks (LANs). Given the size of most servers, the number of clients usually is in the range of hundreds to thousands and the bandwidth required in the 10-100 Mbits/sec range. However, in recent years the servers have grown and the amount of data they are required to handle has grown with them. As a result, the existing I/O architectures need to be modified to support this order of magnitude increase in the bandwidth.
In addition, new Internet applications have increased the demand for improved latency. The adapters must support a larger number of users and connections to consolidate the network interfaces which are visible externally. The combination of all the above requirements presents a unique challenge to server I/O subsystems.
Furthermore, in large environments such as International Business Machines Enterprise System Architecture/390 (Enterprise System Architecture/390 is a registered trademark of International Business Machines Corporation), there are additional requirements that the I/O subsystem must remain consistent with existing support. Applications must continue to run unmodified, and error recovery and dynamic configuration must be preserved or even improved. Sharing of I/O resources must be enabled as well as the integrity of the data being sent or received. This presents new and complex challenges that need to be resolved.
In order to achieve bandwidths which are dramatically higher and still achieve other required challenges, a new system architecture is needed.
This application is being filed on the same day as the following related applications: U.S. applications Ser. No. 09/253,993, 09/255,641, and 09/255,640, all still pending. This application is also related to the following applications filed on Feb. 19, 1999: U.S. applications Ser. No. 09/253,246, 09/253,250, 09/253,247, 09/253,248, 09/252,712, 09/252,552, 09/252,728, 09/252,730, 09/253,101, 09/253,286, 09/252,542, 09/253,249, 09/252,556, 09/252,555, and 09/252,727, all still pending.
SUMMARY OF THE INVENTION
A method and apparatus for error detection in a network computing system having a main storage capable of connecting to at least one application server and an interface element with at least one adapter capable of establishing processing communication with at least one application user(s). Data is transferred across the interface element to and from the main storage. The main storage includes a queuing mechanism providing a plurality of queuing components having attributes of devices to and from which data is to be transferred or received as well as information about the queuing mechanism itself. As part of the queuing component, providing a Storage-List-State Block (SLSB) having state indicators that provide state information about a plurality of buffers that make up each queue. A plurality of Error States is defined by the SLSB Status Block. These Error States are set in the SLSB each time the interface element detects errors in the data stream. By monitoring the number of the errors for a specified time period, it can be determining as whether a session needs to be terminated or kept active.
REFERENCES:
patent: 5491697 (1996-02-01), Tremel et al.
patent: 5802258 (1998-09-01), Chen
patent: 6173355 (2001-02-01), Falik et al.
Hardware Retry Mechanism for Multistage Interconnection Networks for Parallel Computers; IBM TDB; vol. 30, Issue 1; pp. 422-428; Jun. 1987.
Baskey Michael E.
Brice Frank W.
Glassen Steven G.
Hefferon Eugene P.
Ratcliff Bruce H.
Coulter Kenneth R
Gonzalez Floyd A.
International Business Machines - Corporation
Neff Lily
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