Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-04-16
2001-02-27
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S630000, C438S651000, C438S655000, C438S658000, C438S660000, C438S664000, C438S682000, C438S686000, C438S649000, C438S656000, C438S685000
Reexamination Certificate
active
06194315
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to protective metal silicides for use with integrated circuits and methods of making the same, and in particular to silicide liners between a via wall and a metal contact fill.
2. Description of the Related Art
When fabricating integrated circuits (IC), layers of insulating, conducting and semiconducting materials are deposited and patterned in sequence. Contact vias or holes are commonly formed in insulating materials known as interlevel dielectrics (ILDs). The vias are then filled with conductive material, thereby interconnecting electrical devices and wiring at various levels. Similarly, damascene processing involves etching trenches in insulating layers in a desired pattern for a wiring layer. These trenches are then filled with conductive material to produce the integrated wires. Where contact vias, extending downwardly from the bottom of the trenches, are simultaneously filled, the process is known as dual damascene.
Conductive elements, such as gates, capacitors, contacts, runners and wiring layers, must each be electrically isolated from one another for proper IC operation. In addition to interlevel dielectrics surrounding contacts, care must be taken to avoid conductive diffusion and spiking, which can cause undesired shorts between devices and contacts. Protective liners are often formed between via or trench walls and metals in a substrate assembly, to aid in confining deposited material within the via or trench walls. Liners are practically required for certain severe metal deposition processes, such as hot metal reflow and force-fill, particularly in damascene and dual damascene interconnect applications. Protective layers are similarly applied to transistor active areas and other circuit elements to which contacts are formed.
Candidate materials for protective layers should demonstrate good adhesion with materials on either side, such as via walls and metal fillers. Processes should be available for depositing the material with good step coverage into deep, high-aspect ratio vias or trenches. Perhaps most importantly, the liner should serve as an effective diffusion barrier. Typically, liners have been formed of metal nitrides, such as TiN, for which chemical vapor deposition (CVD) processes have been developed. As is known in the art, CVD is particularly well adapted to conformally depositing into deep vias and trenches.
Continued miniaturization of integrated circuits, in pursuit of faster and more efficient circuit operation, results in contact vias having ever higher aspect ratios (defined as the ratio of height to width of the via). Continued scaling of critical device dimensions leads to more narrow contacts, while contact height cannot be proportionately decreased. ILDs must be maintained at a adequate thickness to avoid short circuits and interlevel capacitance, which tends to tie up electrical carriers and slow signal propagation speed. Accordingly, the aspect ratios of contact vias and trenches inevitably increase as circuit designs are scaled down. As is known in the art, high aspect ratio vias and trenches are very difficult to fill conformally, that is, without forming keyholes which can adversely affect conductivity of the contacts.
A conformal liner effectively further increases the aspect ratio, by reducing the narrow width of the via without a proportionate reduction in height. With ever smaller available volume within contact vias, it is desirable to provide thinner via liners, which would not only facilitate filling the via, but would also leave more room for more highly conductive filler metals. Thinning the liner, however, generally reduces the liner's effectiveness in performing its general function of protecting against metal diffusion or spiking, due to the risk of incomplete via wall coverage and the ability of metals and contaminants to more easily diffuse through thin liners.
Conventional liner materials and processes for forming them have been found unsatisfactory for advanced generation fabrication technology, which dictates extremely high aspect ratios and attending harsh metallization processes.
Accordingly, there is a need for improved processes and materials for protective liners in contact vias and runner trenches. Desirably, such processes should also be compatible with conventional fabrication techniques, and thereby easily integrated with existing technology.
SUMMARY OF THE INVENTION
Briefly stated, the present invention provides a thin cobalt silicide layer and a method of forming such a layer as a liner within a high aspect ratio hole.
In accordance with one aspect of the invention, a method is provided for lining a hole, such as a via or a trench, in an integrated circuit. The method includes depositing a silicon layer into the hole. A cobalt seed layer is deposited onto the silicon layer within the hole, and a supplemental cobalt layer is electroplated onto the cobalt seed layer. Thereafter, the cobalt layers are reacted with the silicon layer to form a cobalt silicide liner along the hole sidewalls and floor.
Advantageously, the process creates a liner which can be used with a via having a high aspect ratio. Also, the liner is readily integrated with existing metallization technology, and particularly with newer hot metal and forcefill applications.
In accordance with another aspect of the present invention, a protective liner is provided between a highly conducting metal element in an integrated circuit and an interlevel dielectric. The liner includes a CoSi
x
layer with a thickness of less than about 300 Å.
In accordance with another aspect of the invention, a method is disclosed for forming a protective cobalt silicide layer in an integrated circuit. The method includes providing an undoped, amorphous silicon layer. A cobalt seed layer is deposited over the silicon layer by physical vapor deposition, and an additional cobalt layer electroplated over the cobalt seed layer. The cobalt is then reacted with the silicon layer.
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Hu Yongjun Jeff
Li Li
Gurley Lynne A.
Knobbee, Martens, Olson & Bear, LLP.
Micro)n Technology, Inc.
Niebling John F.
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