Semiconductor processing method of forming a contact opening...

Details Semiconductor processing method of forming a contact opening... Semiconductor processing method of forming a contact opening...

1999-10-13

2001-11-27

Clark, Jhihan B (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

C257S647000, C257S396000, C257S397000, C257S329000, C257S330000, C257S331000, C257S344000, C257S408000, C257S500000

Reexamination Certificate

active

06323540

ABSTRACT:

TECHNICAL FIELD
This invention relates to a semiconductor structure and semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass.
BACKGROUND OF THE INVENTION
Implementing an integrated circuit involves interconnecting electronic devices which are formed on a substrate with other devices on the substrate or the outside world. Typically, such an interconnection is formed by depositing an insulating layer over the substrate and then conducting a contact etch through the insulating layer to a part of a device component thereunder. An example of a part of a device component is a diffusion region which forms a source/drain region in a MOS device.
Typically, when such a contact etch is to be performed, insulating material such as nitride sidewall spacers serve to protect certain device components, such as word lines, from a misalignment of the contact etch. This is commonly referred to as a self-aligned contact etch. Problems arise, however, when such a contact etch is to be conducted over a field isolation mass, such as a field oxide. Such problems are discussed directly below in connection with
FIGS. 1-3
.
FIG. 1
illustrates a semiconductor wafer fragment
10
comprised of a bulk silicon substrate region
12
and a field oxide region
13
. A gate oxide layer
14
overlies silicon substrate
12
. A conductive line
15
overlies gate oxide
14
, and a conductive line
16
overlies field oxide region
13
. Both lines
15
and
16
are provided with an etch resistant cap
17
and sidewall spacers
18
of nitride or some other etch resistant material. Diffusion regions
19
and
20
are provided on either side of line
15
and define source/drain regions to which electrical connection will be made.
Referring to
FIG. 2
, a planarized oxide insulating material
21
is provided over substrate region
12
and patterned with photomask
22
to define a contact opening
23
to diffusion region
20
. As shown, photomask
22
is misaligned somewhat to the left, the effect of which
11
is to provide the contact opening etch directly over field oxide region
13
.
Referring to
FIG. 3
, contact opening
23
has been etched through the oxide insulating material
21
, and due to the photomask misalignment, a portion
24
of field oxide region
13
is also undesirably etched away. Etching away a portion of the field oxide region as shown is undesirable because such may cause shorts to the substrate and leakages which render a device inoperative.
One proposed solution is to provide a thin etch stop layer over the word line and the field oxide region. However, this solution fails when the space through which a contact opening is to be made is very narrow. This is because the thin etch stop layer tends to clog such space and is oftentimes non-uniformly distributed therethrough.
This invention arose out of concerns associated with forming a contact opening to a region adjacent a field isolation mass without the risk of etching the field isolation mass during provision of the contact opening.


REFERENCES:
patent: 4221045 (1980-09-01), Godejahn
patent: 4442591 (1984-04-01), Haken
patent: 4587711 (1986-05-01), Godejahn, Jr.
patent: 4590663 (1986-05-01), Haken
patent: 4746219 (1988-05-01), Holloway et al.
patent: 4980306 (1990-12-01), Shimbo
patent: 5219793 (1993-06-01), Cooper et al.
patent: 5292677 (1994-03-01), Dennison
patent: 5292683 (1994-03-01), Dennison et al.
patent: 5362669 (1994-11-01), Boyd et al.
patent: 5384280 (1995-01-01), Aoki et al.
patent: 5397908 (1995-03-01), Dennison et al.
patent: 5506168 (1996-04-01), Morita et al.
patent: 5539229 (1996-07-01), Noble, Jr. et al.
patent: 5814848 (1998-09-01), Oshima
patent: 5866465 (1999-02-01), Doan et al.
patent: 5986328 (1999-11-01), Liaw et al.
patent: 0 549 055 (1993-06-01), None
patent: 9-134954 (1997-05-01), None
patent: WO 91 10261 (1991-07-01), None

Affiliated with

Also associated with

Rating

Semiconductor processing method of forming a contact opening... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor processing method of forming a contact opening..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor processing method of forming a contact opening... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2615465