Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-09-08
2001-10-30
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S688000, C438S424000, C438S222000
Reexamination Certificate
active
06309958
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and method of manufacturing the same, and more particularly to a semiconductor device and method of manufacturing the same, wherein an insulation film provided with a void space portion is interposed between adjacent ones of a plurality of wirings which are formed on a semiconductor substrate so as to be side by side but not touching.
2. Description of the Related Art
A so-called LSI (i.e., Large Scale Integrated circuit) such as memories, microprocessors and the like known as most typical semiconductor devices makes its individual components minute in size more and more as the integration density of the LSI increases. Under such circumstances, a plurality of wirings formed side by side on a semiconductor substrate are spaced apart from each other at predetermined intervals on the order of submicrons less than or equal to 1 &mgr;m. Adjacent ones of the wirings are isolated from each other through an interlayer insulation film.
However, when the wirings are disposed adjacent to each other through such minute intervals, it is inevitable that an inter-wiring capacitance (hereinafter referred to simply as the capacitance) between these adjacent ones of the wirings increases, which often results in cross talk. As for the magnitude of the capacitance, it depends on the dielectric constant of the material of the interlayer insulation film disposed between the adjacent ones of the wirings. As for a silicon oxide film which is most widely used as the interlayer insulation film, its dielectric constant is within a range of from 3.2 to 3.8. On the other hand, as for the void space portion itself, its dielectric constant is substantially 1.0. In this connection, although it is preferable to form the interlayer insulation film disposed between the wirings from material which is as small as possible in its dielectric constant, it is impossible to use the void space portion itself as the interlayer insulation film, because it is substantially impossible for the void space portion itself to prevent the wirings from being exposed to the external atmosphere.
Under such circumstances, for example, Japanese Laid-open Patent Application No. Hei7-114236 discloses one of conventional semiconductor devices, in which a silicon oxide film containing a plurality of void space portions
53
is used as an interlayer insulation film
54
.
FIG. 5
is a sectional view of the semiconductor device of the above Japanese Patent Publication. As shown in
FIG. 5
, a plurality of wirings
52
are formed side by side on a semiconductor substrate
51
. Disposed adjacent ones of these wirings
52
is the interlayer insulation film
54
formed of the silicon oxide film containing the void space portions
53
. Through this interlayer insulation film
54
, the adjacent ones of the wirings
52
are electrically isolated from each other.
The interlayer insulation film
54
containing these void space portions
53
is easily formed through an appropriate film-forming process such as a so-called high density plasma enhanced CVD process and like processes. In this case, the void space portion
53
is not maintained under vacuum, but contains a small amount of gases produced when the interlayer insulation film
54
is formed. However, it is possible for the void space portion
53
to have its dielectric constant be substantially equal to that of a space maintained under vacuum.
Consequently, in the above conventional semiconductor device, since the void space portion
53
which is small in dielectric constant is interposed between the adjacent ones of the wirings
52
, it is possible for the above conventional semiconductor device to prevent the inter-wiring capacitance from increasing.
On the other hand, in the structure of the conventional semiconductor device shown in
FIG. 5
, in order to decrease the inter-wiring capacitance thereof, it is necessary to have a lower surface
53
a
of the void space portion
53
made substantially flush with a lower surface
52
a
of the wiring
52
. However, since the void space portion
53
is formed as the interlayer insulation film
54
is formed, the actual lower surface
53
a
of the void space portion
53
is formed in a position higher than the lower surface
52
a
of the wiring
52
.
Consequently, in order to make the lower surface
53
a
of the void space portion
53
substantially flush with that
52
a
of the wiring
52
, as shown in
FIG. 6
, the inventor of the subject application has already proposed another conventional semiconductor device in Japanese Laid-open Patent Application No. Hei9-164467. In this another conventional semiconductor device, even when the void space portion
53
is formed as the interlayer insulation film
54
is formed, it is possible to make the lower surface
53
a
of the void space portion
53
substantially flush with that
52
a
of the wiring
52
, as shown in
FIG. 6
, because formation of the interlayer insulation film
54
starts from a bottom surface of a trench
55
of the semiconductor substrate
51
.
A method for fabricating the above another conventional semiconductor device will be now described with reference to
FIGS. 7A
,
7
B and
7
C.
As a first step, as shown in
FIG. 7A
, a metallic wiring film
52
A made of aluminum having a film thickness of approximately 800 nm is formed on the semiconductor substrate
51
through a sputtering process and like processes. After that, the thus formed wiring film
54
A has only its area being formed into wirings covered with a resist film
56
. Then, as shown in
FIG. 7B
, the metallic wiring film
52
is plasma-etched by using the resist film
56
as a mask, so that the wirings
52
are formed into desired patterns.
Finally, as shown in
FIG. 7C
, after the resist film
56
is removed, a so-called etch back is conducted through a plasma etching process to form a plurality of trenches
55
each of which has a depth of approximately 200 nm. Incidentally, the plasma etching process is preferable since it is an excellent means in etching the metallic wiring films or semiconductor materials. After that, the high density plasma enhanced CVD process and like processes are used to form the interlayer insulation film containing the void space portions, so that the above another conventional semiconductor device shown in
FIG. 6
is fabricated.
However, even the another conventional semiconductor device shown in
FIG. 6
suffers from the disadvantage of having the wirings damaged by the electric charge produced from plasma which is used in forming the trenches on the surface of the semiconductor substrate through the plasma etching process.
The above disadvantage will be now described with reference to FIG.
8
. Even after the wirings
52
are formed through the plasma etching process of the metallic wiring film
52
A, the etching process continues to form the trenches
55
. At this time, since the wirings
52
have their side surfaces exposed to the external atmosphere, the electric charge such as excessive electrons and the like resulted from the plasma tends to enter electric conductor elements
57
a
,
57
b
. Here, in the conductor element
57
b
and the like electrically connected with the semiconductor substrate
51
, there is no problem since the electric charge or excessive electrons may escape to the ground.
On the other hand, as for the other conductor element
57
a
which is electrically connected with an insulated-gate electrode
58
of an MOS (i.e., Metal Oxide Semiconductor) type transistor comprising a source region
60
and a drain region
61
, the electrons which enter the conductor element
57
a
are accumulated in the insulated-gate electrode
58
. As a result, a potential difference is developed between the insulated-gate electrode
58
and the semiconductor substrate
51
. Due to the presence of the thus developed potential difference, the gate insulation film
59
is destroyed.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide
Bowers Charles
Hutchins, Wheeler & Dittmar
Huynh Yennhu B.
NEC Corporation
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