Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-09
2001-02-13
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S057000, C257S066000, C257S347000
Reexamination Certificate
active
06188108
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a thin film transistor and a fabricating method thereof which improve device characteristics by forming a substance layer such as a vacuum layer or an air layer, which has a remarkable characteristic of insulation, on an active layer.
2. Discussion of Related Art
As far as a thin film transistor(hereinafter abbreviated TFT) which becomes a crucial part of a pixel array of an active matrix liquid crystal display is concerned, an amorphous silicon layer which enables to be deposited on a wide area as swell as to be produced at a low temperature for a mass production is used for an active layer.
For the present, a driver and a pixel array are required to be integrated simultaneously. There is a certain limitation of electrical mobility of amorphous silicon for a device having a fast operation speed. That's why techniques of fabricating a TFT of low temperature polycrystalline silicon of which electrical mobility is excellent are currently studied.
The methods of forming a polycrystalline silicon layer are largely divided into a high temperature process which deposits silicon of a polycrystalline state and a low temperature process which deposits amorphous silicon and then crystallizing the amorphous silicon into a polycrystalline state by annealing. In the latter method, after an amorphous silicon layer has been deposited at around 350 C., the amorphous silicon layer is crystallized by applying energy such as laser. The crystallization of silicon proceeds by growing silicon grains. One silicon grain collides into another grains nearby to terminate its growth so that grain boundaries are generated among the silicon grains.
FIG. 1A
to
FIG. 1D
show cross-sectional views of fabricating a TFT according to a related art.
Referring to
FIG. 1A
, after a buffer layer
10
of silicon oxide or silicon nitride has been formed on an insulated substrate
100
, an amorphous silicon layer is deposited on the buffer layer
10
. Then, the amorphous silicon layer is crystallized by laser energy. An active layer
12
is formed by patterning the crystallized silicon layer by photolithography.
Referring to
FIG. 1B
, an insulating layer and an electrically-conductive layer are deposited successively on the active layer
12
. A gate electrode
15
is patterned by etching the electrically-conductive layer by photolithography. A gate insulating layer
13
is patterned by etching the insulating layer in use of the gate electrode
15
as an etch mask.
Referring to
FIG. 1C
, a source region
12
S and a drain region
12
D as impurity regions are formed by doping the exposed surface of the active layer
12
with impurities. An unexplained sign of ‘
12
C’ indicates a channel region.
Referring to
FIG. 1D
, a protecting layer
16
is deposited over a whole surface of the substrate. Contact holes exposing portions of the source and drain regions
12
S and
12
D are formed by etching predetermined portions of the protecting layer
16
by photolithography. After an electrically-conductive layer has been deposited over the substrate, a source electrode
17
S and a drain electrode
17
D are formed by etching the electrically-conductive layer by photolithography.
As mentioned in the above description, a polycrystalline silicon layer is formed by depositing an amorphous silicon layer on an insulated substrate at low temperature and by crystallizing the amorphous silicon layer by the irradiation of a laser beam thereon.
Once the laser beam is irradiated to the amorphous silicon layer, most of the beam energy is absorbed by the amorphous silicon layer. Thus, the silicon layer is liquidized selectively or completely. Then, the liquidized silicon layer is cooled immediately. In this process, the remaining or generated silicon particles work as crystallizing nuclei. In this case, the silicon is crystallized by the growth of silicon grains. The growth of each silicon grain is terminated by the collisions of the neighbouring grains wherein the collisions generate grain boundaries.
The existence of the boundaries in a polycrystalline silicon layer results in a rugged surface of the silicon layer. Thus, an active layer of which surface is not smooth is formed. Thereby, a gate insulating layer of which surface is contacted with the active layer shows a poor interface characteristic. Such poor interface characteristic between the active layer and the gate insulating layer causes the increases of breakdown of the thin layer, a flat band shift and an S-factor so that the characteristics of a TFT may be ruined.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a thin film transistor and a fabricating method thereof that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
The object of the present invention is to provide a thin film transistor and a fabricating method thereof by forming a space between a channel region and a gate insulating layer to improve an interface characteristic between an active layer and the gate insulating layer, thereby improving device characteristics.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes an insulated substrate, an active layer on the insulated substrate wherein the active layer has a source region, a channel region and a drain region, a gate insulating layer having an inner space on the channel region, and a gate electrode on the gate insulating layer over the channel region.
In another aspect, the present invention includes the steps of forming an active layer on an insulated substrate, forming a gate insulating layer having an inner space on the active layer, forming a gate electrode on the gate insulating layer, and forming a source region and a drain region in the active layer by doping the substrate including the active layer with impurities.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5371398 (1994-12-01), Nishihara
patent: 5767531 (1998-06-01), Yoshinouchi
patent: 6075257 (2000-06-01), Song
Moon Dae-Gyu
Yoon Jin-Mo
LG. Philips LCD Co. Ltd.
Long Aldridge & Norman LLP
Ngo Ngan V.
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