Computer graphics processing and selective visual display system – Computer graphics display memory system – Plural storage devices
Reexamination Certificate
1999-01-04
2001-10-02
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Plural storage devices
C345S215000, C345S531000
Reexamination Certificate
active
06297832
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to video graphics processing and more particularly to a method and apparatus for memory access scheduling in a video graphics system.
BACKGROUND OF THE INVENTION
Video information and rendered graphical images are being combined in an increasing number of applications. Examples include animated icons, on screen menus, video windows in a graphical display, etc. As increasingly integrated systems are developed, common circuitry within the systems must satisfy the needs of both the graphical image processing and the video image processing. One example of such a shared resource is memory.
Graphical information is typically stored in memory in a linear format. In a linear format, data is typically stored sequentially in a localized portion of the memory and accessed in a similar sequential manner. Video information, however, is often stored in a tiled format that allows small, localized portions of a video image to be accessed more rapidly. In an integrated video graphics system, both of these formats must be supported by the circuitry that controls memory accesses.
Because the video information and the graphical information are processed and displayed concurrently, it is important that the two types of data are able to be stored and retrieved from the memory in an efficient manner. One of the problems that arises in storing and retrieving these different types of data from memory is the timing penalties associated with page faults. A page fault occurs when a read or write to one page in memory is immediately followed by a read or write to a different page in the memory block. In order to prepare the memory for the access to the new memory block, additional time must be incurred. In the situation where there is frequent toggling between different memory clients within the video graphics system, each of which may be accessing data on different pages, it is important to try and mask or hide the timing penalties associated with these page faults.
In prior arts systems, linear memory clients typically stored large blocks of linear data within a single page of the memory. Tiled clients typically perform scattered accesses to smaller portions of the memory, each of which may be located on a separate page. In this prior art situation, it is very difficult to hide page faults because all of the accesses are occurring within a single block or portion of the memory. Thus, in most cases, when a client began a new access to the memory, the timing penalties associated with a page fault would be incurred.
In mixed video graphics systems, real time video is often displayed. In such situations, it is very important that the memory accesses that retrieve both video and graphical information for display are as efficient as possible in order to insure that video frames are not dropped or rendered in a corrupted manner. In such situations, the penalties associated with page faults are very detrimental to the operation of the system. Although one solution to the problem associated with page faults is to add additional memory blocks or increase the bandwidth of the memory to compensate for the penalties, these solutions add cost and complexity to the system, thus removing some of the benefits of integration.
Therefore a need exists for a method and apparatus for sequencing memory accesses such that the penalties associated with page faults are avoided or effectively hidden when they are unavoidable.
REFERENCES:
patent: 5664162 (1997-09-01), Dye
patent: 5793693 (1998-08-01), Collins et al.
patent: 5912676 (1999-06-01), Malladi et al.
patent: 5937204 (1999-08-01), Schinnerer
patent: 6064407 (2000-05-01), Rogers
patent: 6204863 (2001-03-01), Wilde
Chow Paul
Mizuyabu Carl K.
Swan Philip L.
Wang Chun
ATI International SRL
Tung Kee M.
Vedder Price Kaufman & Kammholz
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