Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1998-07-17
2001-10-23
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S819000
Reexamination Certificate
active
06308297
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to memory address checking in computer systems.
Computer systems typically include mechanisms for ensuring the correctness of data, for example through the use of parity and error correction codes. Such mechanisms are often applied to the data paths between processing elements, I/O elements and main memory. Indeed, it is common for parity or error correction codes to be stored along with data in main memory. As a result of this the parity or error correction codes are available to check the validity of data when subsequently read from memory. Accordingly, it is possible for the validity and correctness of data to be verified at all stages along the data path from the processing elements to memory and back again.
It is also known to employ parity or error correction codes for ensuring the correctness of addresses on an address bus. However, the protection provided by the use of such codes for checking addresses effectively stops at the entry to the memory subsystem, such that address errors within the memory subsystem can go undetected.
Accordingly, an aim of the present invention is to improve the degree of security of memory operation in a computer system.
SUMMARY OF THE INVENTION
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims.
In accordance with one aspect of the invention, there is provided a solid state memory device including a plurality of addressable memory locations. During operation of the memory device, an address port receives an address identifying at least one memory location and associated verification information for verifying the address. Decoding logic is connected (directly or indirectly) to the address port and is operable to respond to an address received at the address port to decode the address. Verification logic is connected (directly or indirectly) to the address port and is operable to respond to an address and associated verification information received at the address port to verify the received address.
By providing address verification within a solid state memory device, it is possible to extend the verification of addresses into the memory devices themselves. Previously, address verification was only possible externally to solid state memory devices. In this manner, the addresses can be checked from the point of encoding to the point of decoding within a computer system.
By providing a memory device in accordance with the invention it is possible to ensure a higher security of operation of a computer system incorporating such a memory device, as errors which might develop or be present due to incorrect assembly between a memory controller and individual memory devices can be detected. Also, an embodiment of the invention can be used to verify overall reliability of a system. For example, it would be possible to strobe a memory chip at higher and higher clock rates until a fault is detected, for example due to capacitive or other effects inside or between the memory system devices, thus establishing reliable operating parameters for a memory system and a computer system incorporating such memory devices.
The verification logic can be configured in different ways. For example, it can be configured to be operable to prevent access to the memory locations where address verification is negative. Alternatively, or in addition, in the case of a read operation the verification logic is operable to prevent output from the device of the content of an addressed memory location where address verification is negative. Alternatively, or in addition, in the case of write operation the verification logic is operable to prevent modification of the content of an addressed memory location where address verification is negative. It can also be configured to be operable to inhibit the output of the decoding logic where address verification is negative. Generally, however, the verification logic is operable to prevent modification of any memory location where address verification is negative.
Preferably, the verification logic is operable to indicate an error where address verification is negative. More preferably, the memory device comprises an error output for returning an error signal where address verification is negative. The error signal can be used simply to report a fault. Alternatively, it can be used to cause a memory controller to retry a memory addressing operation.
The verification information could comprise an error detecting code such as, for example, one or more parity bits. Alternatively, or in addition, the verification information could comprise an error correcting code. In this latter case, the verification logic could be configured to correct an invalid address based on the error correcting code, where possible.
Preferably, the address port comprises a plurality of device contacts for connection to a bus or to control lines to a memory controller. A data port can be provided for receiving write data associated with a received address and a data register can be provided for holding write data pending verification of the received address. Where the data is also associated with data verification information, the verification logic can be operable to verify that data and to prevent writing of data to the memory where verification is negative.
In a preferred implementation, the memory device is an integrated memory chip. The integrated memory device can comprise a plurality of memory banks. The verification and decoding logic can be provided at one or more levels within the device, for example down to the memory bank level.
In accordance with another aspect of the invention, there is provided a solid state memory device comprising a plurality of addressable memory locations, a data port for receiving data for storage in at least one memory location including associated data verification information for verifying the data, and verification logic responsive to received data and data verification information to verify the received data and to prevent storage of that data where verification is negative. Thus controlled storage can be made dependent upon the validity of received data.
In accordance with a further aspect of the invention, there is provided a computer system. The computer system includes a processing unit, a bus connected to the processing unit and including address lines and verification information lines for an address and associated verification information, a memory controller connected to the bus and at least one solid state memory device as described above and connected to the memory controller. The bus can include an error line for an error signal or provision for a negative acknowledgement indicative of a negative address verification at the memory device.
In accordance with a further aspect of the invention, there is provided a method of addressing a memory location within a solid state memory device comprising: receiving an address at the memory device with associated verification information for verifying the address; and verifying the received address within the memory device.
REFERENCES:
patent: 5173905 (1992-12-01), Parkinson et al.
patent: 5291584 (1994-03-01), Challa et al.
patent: 5392302 (1995-02-01), Kemp et al.
patent: 5463635 (1995-10-01), Kumazawa et al.
patent: 5615148 (1997-03-01), Yamamura et al.
patent: 5675540 (1997-10-01), Roohparvar
patent: 5805510 (1998-09-01), Miyakawa et al.
patent: 5978953 (1999-11-01), Olarig
patent: 5991517 (1999-11-01), Harari et al.
patent: 6052781 (2000-04-01), Weber
Chase Shelly A
De'cady Albert
O'Melveny & Myers LLP
Sun Microsystems Inc.
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