Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-02-24
2001-02-20
Lefkowitz, Sumati (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C361S058000
Reexamination Certificate
active
06192435
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an interface between a peripheral unit, which is powered by electric current fed from a main unit, and the main unit, and more particularly to an interface circuit which allows connection/disconnection of the peripheral unit to/from the main unit during the electrical operation of the main unit (i.e. when the main unit is switched on).
2. Description of the Prior Art
Currently, many combinations exist of a main electronic unit and a peripheral unit which is removably attached to the main unit. One example of such a combination is a computer and an optional card. In this example, the computer is a main unit and the optional card is a peripheral unit.
Peripheral units include not only those that are easily inserted/removed by a user, such as a PCMCIA card, but also a redundant circuit card for a highly reliable computer system, which is attached/detached only by a maintenance operator. In the former case, insertion or removal of the peripheral unit tends to occur while the main unit is powered on (hereinafter, referred to as “hot line connection/disconnection” or “hot line insertion/extraction”), due to the fact that ordinary users lack sufficient knowledge about the electronic apparatus. Nevertheless, such an action is naturally not recommendable. On the other hand, the latter often necessitates hot line connection/disconnection in order to avoid taking the system down. Either case requires some countermeasures for avoiding malfunction in the main unit or electrical damage to the main and peripheral unit.
JPA H6-161606 discloses an interface effective for such hot line insertion/extraction of the peripheral unit to/from the main unit (hereinafter referred to as a prior art system), which is illustrated in FIG.
8
.
In this figure, numeral
2
designates a backboard of a main unit, and numeral
3
designates a substrate which corresponds to a peripheral unit. The backboard
2
(i.e. the main unit) is operated by a power supply voltage V.
The substrate
3
contains a field-effect transistor (FET)
10
for controlling opening and closing of an electric current feeding path, a buffer resistor R
3
which ensures steady electric current flow during the OFF state of the FET
10
to prevent an abrupt change in electric current caused by ON/OFF operation of the FET
10
, and a delay circuit consisting of resistors R
1
, R
2
, and a capacitor C
1
. The delay circuit is employed for delaying the start of the electrical feed when the substrate
3
is inserted into the backboard
2
. After a predetermined delay from the insertion of the substrate
3
, which is defined by a time constant of the delay circuit, the base voltage of the FET
10
falls to a potential determined by the dividing resistors R
1
and R
2
and constant electric current feeding is carried out.
The substrate
3
also contains a delay inhibiting circuit
18
for prohibiting delay generated by the delay circuit, which comprises a photocoupler (PC
1
) and a resistor R
4
. When electric current flows into the LED of the photocoupler PC
1
, the transistor of the photocoupler is turned ON, making the voltage across the capacitor
1
zero, which prohibits the delay generation. During this operation, the resistor R
4
controls the electric current flowing into the LED.
During the normal operation, the substrate
3
receives an electrical supply through the FET
10
, where the input voltage of the FET
10
is Vi. The symbol Vi is only for convenience, and is in fact substantially equal to the source voltage V. On the other hand, the output voltage of the FET
10
is connected to a predetermined load circuit (not shown), and thus, the substrate
3
functions as a peripheral unit.
The substrate
3
further includes a connector for connection with the backboard
2
. The connector has a long terminal set, the pin contact of which is relatively long, and a short terminal. The long terminal set includes source terminals and ground terminals and is connected to the corresponding terminal set of the backboard
2
. One end of the short terminal is grounded to a signal ground (SG) terminal of the backboard
2
, and the other end is connected to the delay inhibiting circuit
18
of the substrate
3
. In this structure, even when only a long terminal set is connected to the backboard
2
, the source of the FET
10
(with a voltage Vi) is grounded via the resistors R
1
, R
2
and R
4
, and is connected to the load circuit via the resistor R
3
, thereby securing electrical current flow in spite of the disconnected state of the short terminal.
The action of electrical current supply in such a prior art structure will be described in more detail.
(i) Insertion (Attaching) of the Substrate
When inserting the substrate
3
, the long terminal set is first connected with the corresponding terminal set of the backboard
2
and the ground terminals are connected to the SG terminals of the backboard
2
, whereby the voltage Vi becomes equal to the source voltage V. Electric current is supplied to the resistors R
1
and R
2
. However, the FET
10
is not turned ON yet at this stage, because the electric current flows via the resistor R
4
into the LED of the photocoupler PC
1
in the delay inhibiting circuit
18
, which puts the transistor of the PC
1
in the ON state, resulting in that the voltage across the capacitor C
1
becomes equal to zero and the source gate voltage Vgs of the FET
10
becomes 0.
The short terminal then is connected with the corresponding SG of the backboard
2
, and the input to the LED of the PC
1
is connected to SG. No electric current flows into the LED and the transistor of the PC
1
is turned off. Both ends of the capacitor C
1
become open, and the charge by Vi to the capacitor is started. The time constant of the delay circuit at this time is represented as the following equation.
C=R
1
*
R
2
*
C
1
/(
R
1
+
R
2
) (1)
During this operation, the source gate voltage Vgs of the FET is gradually increased, and when a delay time defined by the order of the time constant has passed, the FET
10
is turned ON. Namely, after a predetermined time from the connection of the short terminal, regular electric supply is started. Generally, electric current flowing through the FET
10
increases as Vgs increases, and therefore, the output voltage of the FET
10
increases with a gentle slope as the time constant becomes larger.
In this manner, electric feeding can be gradually increased with the hot line insertion of the substrate
3
. However, in reality, the increase of the electric feeding can not be uniformly achieved due to the presence of the resistor R
3
, since the resistor R
3
starts feeding electric current to the substrate
3
upon connection of only the long terminal set. The presence of the resistor R
3
is rather more important for extraction (detaching) of the substrate
3
than for insertion thereof, as will be described below.
(ii) Extraction of the Substrate
When the extraction of the substrate
3
is started, the short terminal is first detached from the backboard
2
. Namely, the LED of the PC
1
is disconnected from SG of the backboard
2
, the transistor of the PC
1
is turned on, and both ends of the capacitor C
1
are short-circuited. The voltage across the capacitor C
1
becomes zero, and Vgs of the FET
10
drops instantly and the transistor is immediately turned off. Thus, among the electric supply paths extending to the substrate
3
, the current path from the FET
10
is instantaneously shut off, and only the electric current supply via the resistor R
3
remains, which is also finally shut off by the disconnection of the long terminal set.
During the extraction of the substrate
3
, the electric current supply is lowered in the final state through two stages, similar to the insertion operation, but the fluctuation in the electric feeding caused by the ON-OFF operation of the FET
10
is larger than that in the insertion operation. This means that, in such a prior art structure, the resistor R
3
functions
Lefkowitz Sumati
Mitsubishi Denki & Kabushiki Kaisha
Rothwell Figg Ernst & Manbeck
LandOfFree
Apparatus for allowing smooth hot insertion and removal of a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus for allowing smooth hot insertion and removal of a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for allowing smooth hot insertion and removal of a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2613408