System including a ferroelectric memory

Details System including a ferroelectric memory System including a ferroelectric memory

2000-05-26

2001-11-20

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

06321360

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a system including a nonvolatile semiconductor memory which uses a ferroelectric material. More specifically, the invention relates to a system including a ferroelectric memory that decreases the probability of erroneous operation of the memory.
BACKGROUND OF THE INVENTION
A memory using a ferroelectric material, e.g., a ferroelectric random access memory (FERAM) is a nonvolatile memory which stores data based upon the direction of polarization of the ferroelectric material. In a ferroelectric memory, for example, a memory cell includes a ferroelectric capacitor and a switching transistor. The stored data is read out by applying a voltage to the ferroelectric capacitor in such a manner that the polarization is oriented in one direction and by determining whether the polarization at this moment is inverted or not. Such a ferroelectric memory is disclosed in, for example, IEEE International Solid-State Circuits Conference, DIGEST OF TECHNICAL PAPERS, 1994, pp. 268-269.
In ordinary operation, on the other hand, the ferroelectric memory may be used as a dynamic random access memory (DRAM) by fixing a plate potential of the ferroelectric capacitor to, for example, a power source voltage. When the power source is turned off, however, the operation is performed, in which the data of the stored potential is converted into data of the direction of polarization of the ferroelectric material. This makes it possible to hold the data even after the power source is turned off. Such a ferroelectric memory is disclosed in, for example, Symposium on VLSI Technology, DIGEST OF TECHNICAL PAPERS, 1990, pp. 15-16.
SUMMARY OF THE INVENTION
In an ordinary DRAM, it is generally known that erroneous operation results from the stored data being inverted by a noise charge that is generated by radioactive rays. It is considered that such a stored data inversion phenomenon also takes place with a ferroelectric memory when it is operated as an ordinary DRAM. For a ferroelectric memory system that detects the direction of polarization, the polarization is oriented in one direction when the data is to be read out and the polarization data then extinguishes. Therefore, the polarization data must be written again based upon the data that is read out before the operation for reading the data is finished. When the data is incorrectly read out due to noise, the polarization is incorrectly written again, too. In such a case, the error is called a soft error, i.e., an error caused by erroneous inversion of the stored data due to radioactive rays or noise. It is called a soft error because the function of the memory cell has not been lost.
A soft error in a ferroelectric memory may trigger a serious problem compared to that of the case of a DRAM for the following reasons.
In case the system has halted due to the occurrence of an error in the data stored in the memory such as a DRAM, the system can at least be restarted. In many cases, however, the data which is sorted in a nonvolatile memory such as a ferroelectric memory is used repetitively, for example, in an OS (operating system) of the system. For portable electronic components, in particular, if the OS of the system or the application program is stored in a ferroelectric memory, then, there is no need of using a large nonvolatile storage medium such as hard disk. Accordingly, a compact system can be built. Furthermore, the CPU can access the ferroelectric memory at speeds higher than those of accessing the hard disk and, hence, the start time of the portable electronic components can be significantly decreased.
In a system including such a ferroelectric memory, if a soft error occurs even once in the ferroelectric memory, erroneous data is written again generating the potential for a serious defect in the functions of the system and often triggering a shut down of the system. To recover the system in such a case, the correct data of the OS, for example, must be written again into the ferroelectric memory, usually by connection to an external nonvolatile storage medium such as a hard disk. This is quite inconvenient for portable electronic components that are used in a variety of places such the function of the system remains halted until the nonvolatile storage medium such as a hard disk is obtained and connected.
In order to avoid soft errors in the DRAM, a method has been employed to automatically detect and correct soft errors by providing an error checking and correcting circuit (ECC circuit). In a large-scale system such as large computer, the ECC circuit can be provided in a chip separate from the main body. In a small-scale system such as a portable electronic component or a personal computer, however, it is desirable that the DRAM chip itself is provided with an error checking and correcting function to make the system compact. A DRAM chip having an error checking and correcting function has been disclosed in IEEE International Solid-State Circuits Conference, DIGEST OF TECHNICAL PAPERS, 1987, pp. 22-23.
Reference is made to the prior art diagrams of
FIGS. 8A and 8B
. In particular,
FIG. 8A
is a diagram showing a fundamental constitution of a DRAM mounting an ECC circuit and the diagram of
FIG. 8B
is a flow chart of the writing/reading operations.
FIG. 8A
shows a DRAM
80
that has a memory cell array
81
and a peripheral circuit portion
84
. The data stored in the memory cell array
81
can be classified into two types, i.e., data storage bits
82
for storing data and parity bits
83
. The peripheral circuit portion
84
includes an ECC circuit
85
.
When the data are to be written (step
91
) as shown in the flow chart of the diagram
FIG. 3B
, the parity bit data are formed (step
92
), and the data storage bits and parity bits are written into the DRAM
80
(step
93
). To read the data (step
95
), first, a plurality of data storage bits and corresponding parity bits are read out (step
96
). Relying upon t6he results of the operation for these data, the ECC circuit
85
determines whether or not an error has occurred for any bit and for any bit in which the error has occurred, corrects the data (step
97
), and sends the data from the DRAM to the CPU (step
98
). Thus, there is realized a DRAM which does not erroneously operate for the CPU.
In a conventional DRAM having an ECC circuit incorporated in the chip, however, (1) the writing speed decreases since a parity bit must be formed for each writing, (2) the reading speed decreases since the parity bit must be read together with the stored data and the ECC checking must be executed to correct error for each reading, and (3) the chip size increases by the area of the ECC circuit resulting in an increase in the cost of the chip. Accordingly, almost none of the DRAMs that have been placed on the market incorporate an ECC. This results from the consideration of achieving a balance between the potential for damaging the system in the case of soft error in the DRAM, the frequency of occurrence of soft error and the extent to which the above-mentioned drawbacks affect the DRAM when an ECC circuit is incorporated in the chip.
In the ferroelectric memory, on the other hand, it is expected that soft errors may cause a more serious type of damage to the system on account of the reasons described above. Further, when an ECC circuit is mounted as on the DRAM chip to prevent soft errors from occurring, problems arise with respect to the operation speed, which decreases. Also the cost of the chip increases when the memory is fabricated with an ECC.
An object of the present invention is to provide a system including a ferroelectric memory, which has a low probability of causing serious damage to the system that may result from a soft error in the ferroelectric memory. It is also an object of the invention to provide a system including a ferroelectric memory that does not cause the operation speed to decrease and does not increase the cost of the chip, as a result of solving the above-mentioned problems.
(a) In order to accomplish the above-mentio

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