Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-06-11
2001-02-27
Hardy, David (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S532000
Reexamination Certificate
active
06194758
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more specifically, it relates to a semiconductor device comprising a capacitor and a method of fabricating the same.
2. Description of the Prior Art
In recent years, high integration and refinement are increasingly required to a semiconductor device, particularly a semiconductor memory device such as a DRAM (dynamic random access memory).
FIG. 114
is a typical plan view showing a part of a memory cell region of a conventional DRAM. Referring to
FIG. 114
, the memory cell region of the conventional DRAM comprises a capacitor including a field-effect transistor and capacitor lower electrodes
1170
a
and
1170
b,
word lines
1043
a,
1043
b,
1043
e
and
1043
f
and a bit line
1174
. The field-effect transistor is formed by the word lines
1043
a
and
1043
e
serving as gate electrodes and an active region
1039
serving as a source/drain region. In more concrete terms, the active region
1039
is formed in a major surface of a semiconductor substrate, and the word lines
1043
a,
1043
b,
1043
e
and
1043
f
are formed on the major surface of the semiconductor substrate. A first interlayer isolation film (not shown) is formed on the word lines
1043
a,
1043
b,
1043
e
and
1043
f
and the major surface of the semiconductor substrate. The bit line
1174
is formed on the first interlayer isolation film substantially perpendicularly to the word lines
1043
a,
1043
b,
1043
e
and
1043
f.
A second interlayer isolation film (not shown) is formed on the bit line
1174
and the first interlayer isolation film. The capacitor lower electrodes
1170
a
and
1170
b
are formed on the second interlayer isolation film. The bit line
1174
is electrically connected with the active region
1039
through a contact hole
1049
. The capacitor lower electrodes
1170
a
and
1170
b
are electrically connected with single ones of source/drain regions of the field-effect transistor in the active region
1039
through contact holes
1038
a
and
1038
b
respectively.
FIG. 115
is a sectional view of the memory cell region of the DRAM taken along the line
500
—
500
in FIG.
114
.
FIG. 115
is a sectional view showing the section taken along the line
500
—
500
in
FIG. 114 and a
section of a peripheral circuit region of the DRAM. Referring to
FIG. 115
, source/drain regions
1201
a
and
1201
b
of the field-effect transistor are formed on the active region
1039
enclosed with a trench isolation oxide film
1040
in the memory cell region of the DRAM. A gate electrode
1043
a
is formed on a channel region held between the pair of source/drain regions
1201
a
and
1201
b
through a gate insulating film
1042
a.
A silicon nitride film
1044
a
is formed on the gate electrode
1043
a.
The gate electrode
1043
a
consists of n-type doped polysilicon. Side walls
1046
a
and
1046
b
consisting of silicon nitride films are formed on side surfaces of the gate electrode
1043
a
and the silicon nitride film
1044
a.
A non-doped silicon oxide film
1047
is formed on the side walls
1046
a
and
1046
b,
the silicon nitride film
1044
a
and a major surface of a semiconductor substrate
1001
. A gate electrode
1043
b
is formed on the trench isolation oxide film
1040
through a gate insulating film
1042
b.
A silicon nitride film
1044
b
is formed on the gate electrode
1043
b.
Side walls
1046
c
and
1046
d
consisting of silicon nitride films are formed on side surfaces of the gate electrode
1043
b
and the silicon nitride film
1044
b.
The non-doped silicon oxide film
1047
is formed on the side walls
1046
c
and
1046
d
and the silicon nitride film
1044
b.
A first interlayer isolation film
1048
is formed on the non-doped silicon oxide film
1047
. The contact hole
1049
is formed by partially removing the first interlayer isolation film
1048
and the non-doped silicon oxide film
1047
by etching. A doped polysilicon film
1052
is formed in the contact hole
1049
and on the first interlayer isolation film
1048
. A refractory metal silicide film
1053
is formed on the doped polysilicon film
1052
. The doped polysilicon film
1052
and the refractory metal silicide film
1053
form the bit line
1174
. A silicon nitride film
1054
is formed on the refractory metal silicide film
1053
. Side walls
1055
a
and
1055
b
consisting of silicon nitride films are formed on side surfaces of the silicon nitride film
1054
, the refractory metal silicide film
1053
and the doped polysilicon film
1052
. A second interlayer isolation film
1037
is formed on the first interlayer isolation film
1048
, the side walls
1055
a
and
1055
b
and the silicon nitride film
1054
. The first and second interlayer isolation films
1048
and
1037
are partially removed, thereby forming the contact hole
1038
a
for electrically connecting the capacitor lower electrode
1170
a
with one of the source/drain regions
1201
a
and
1201
b.
A plug
1057
consisting of doped polysilicon is formed in the contact hole
1038
a.
The capacitor lower electrode
1170
a
is formed in the contact hole
1038
a
and on the second interlayer isolation film
1037
. The capacitor lower electrode
1170
a
has a cylindrical structure, in order to ensure the capacitance of the capacitor with a small occupied area. A dielectric film
1150
is formed on the capacitor lower electrode
1170
a
and the second interlayer isolation film
1037
. A capacitor upper electrode
1151
is formed on the dielectric film
1150
. A third interlayer isolation film
1205
is formed on the capacitor upper electrode
1151
.
The peripheral circuit region is provided with the field-effect transistor and a wiring layer
1202
which are elements forming peripheral circuits. Source/drain regions
1201
d
and
1201
e
are formed on the major surface of the semiconductor substrate
1001
. Gate electrodes
1043
c
and
1043
d
are formed on channel regions which are adjacent to the source/drain regions
1201
d
and
1201
e
through gate insulating films
1042
c
and
1042
d
respectively. Silicon nitride films
1044
c
and
1044
d
are formed on the gate electrodes
1043
c
and
1043
d.
Side walls
1046
e
to
1046
g
consisting of silicon nitride films are formed on side surfaces of the gate electrodes
1043
c
and
1043
d
and the silicon nitride films
1044
c
and
1044
d.
The non-doped silicon oxide film
1047
is formed on the major surface of the semiconductor substrate
1001
, the silicon nitride films
1044
c
and
1044
d
and the side walls
1046
e
to
1046
g.
The first interlayer isolation film
1048
is formed on the non-doped silicon oxide film
1047
. The first interlayer isolation film
1048
is partially removed, thereby forming contact holes
1050
and
1051
. The doped polysilicon film
1052
is formed on the first interlayer isolation film
1048
and in the contact holes
1050
and
1051
. The refractory metal silicide film
1053
is formed on the doped polysilicon film
1052
. The doped polysilicon film
1052
and the refractory metal silicide film
1053
form the wiring layer
1202
in the peripheral circuit region. A silicon nitride film
1203
is formed on the refractory metal silicide film
1053
. Side walls
1204
a
and
1204
b
consisting of silicon nitride films are formed on side surfaces of the silicon nitride film
1203
, the refractory metal silicide film
1053
and the doped polysilicon film
1052
. The second interlayer isolation film
1037
is formed on the first interlayer isolation film
1048
, the silicon nitride film
1203
and the side walls
1204
a
and
1204
b.
The dielectric film
1150
of the capacitor extending from the memory cell region is formed on the second interlayer isolation film
1037
. The capacitor upper electrode
1151
is formed on the dielectric film
1150
. The third interlayer isolation film
1205
is formed on the second interlayer isolation film
1037
and the capacitor upper electrode
1151
.
FIG. 116
illustrat
Arima Hideaki
Shimizu Masahiro
Tanaka Yoshinori
Hardy David
Mitsubishi Denki & Kabushiki Kaisha
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