Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-08-19
2001-10-30
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C712S010000, C712S011000, C714S030000, C714S724000, C714S732000
Reexamination Certificate
active
06311311
ABSTRACT:
FIELD OF THE INVENTION
This invention pertains to the field of computer systems. Particularly, verification of the implementation of a processor architecture via comparison of actual and expected results of architected registers after the execution of instruction streams, particularly where there are many instructions in the stream, creating long instruction streams.
Trademarks: S/390 and IBM are registered trademarks of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
BACKGROUND
Within IBM, the mainframe designs have chips with logic testing registers called Multiple Input Shift Register (MISR) which were provided for various manufacturing tests to test for quality assurance of the hardware. Another use of multiple input shift registers is for error checking in processors where data is partitioned across one or more chips. U.S. Pat. No. 5,784,383 illustrates a method, unrelated to the present solution used for functions testing, which uses a Multiple Input Shift Register (MISR) which permits detecting of errors across chip boundaries due to a hardware failure in control logic even though a processor's error checking code (ECC) is not bad. A Multiple Input Shift Register (MISR) on each bus is used to collect a dynamic signature representing all the critical buses on each chip that need to be compared. The MISR state combines present and previous states of these buses, so for the testing in accordance with the method of U.S. Pat. No. 5,784,383 the MISR will be different if one or more bus controls break or are broken. Since an N-bit MISR shifts, comparing a single bit of the MISR each cycle guarantees detection within N cycles of a problem. The method of U.S. Pat. No. 5,784,383 for identifying errors includes accumulating bus signature information which is a function of current and previous values of an input bus structures to determine sync of buses.
Functional testing for verification of functional design of processors is partly done by comparing the actual to expected values of architected registers after simulation of test instruction streams consisting of a few to many instructions. Until the present, this type of functional verification has been incomplete for cases where an instruction in a test instruction stream updates a register incorrectly due to a functional design problem, but the problem is not detected because the incorrect register value is overwritten by a subsequent instruction in the test instruction stream before being used as a source operand. The comparison of actual to expected results at the completion of the simulation of the entire test instruction stream does not detect this functional error since the incorrect interim register value is not observed and does not affect the final register value. There is a desire to improve the functional verification of processors by having all interim register values of test instruction streams checked, although still only comparing actual to expected values at the completion of the simulation of the test instruction stream.
SUMMARY OF THE INVENTION
In accordance with our preferred embodiment, we have provided a method for improving functional testing for verification of functional design of processors by using a Multiple Input Shift Register (MISR) to make all updates to all architected registers during the execution of a test instruction stream observable. This method overcomes the problem that some interim values which appeared during functional instruction stream testing would be overwritten by subsequent instructions in a test instruction stream without being used as source operands, so that the final values did not depend on these interim values and are thus not checked.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description and to the drawing.
REFERENCES:
patent: Re. 31828 (1985-02-01), Raymond et al.
patent: 4216539 (1980-08-01), Raymond et al.
patent: 5347652 (1994-09-01), Epstein et al.
patent: 5590345 (1996-12-01), Barker et al.
patent: 5638382 (1997-06-01), Krick et al.
patent: 5734921 (1998-03-01), Dapp et al.
patent: 5784383 (1998-07-01), Meaney
patent: 5978946 (1999-11-01), Needham
patent: 6055660 (2000-04-01), Meaney
patent: 6065106 (2000-05-01), Deao et al.
Roche, P., Logic Signature Application, IBM Tecchnical Disclosure Bulletin, Vol. 27, No.8, Jan., 1985, pp. 4943-4944.
Huott William V.
Swaney Scott B.
Wile Bruce
Augspurger Lynn L.
International Business Machines - Corporation
Smith Matthew
Speight Jibreel
LandOfFree
Multiple input shift register (MISR) signatures used on... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multiple input shift register (MISR) signatures used on..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple input shift register (MISR) signatures used on... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2611469