Power saving methods for programmable logic arrays

Details Power saving methods for programmable logic arrays Power saving methods for programmable logic arrays

1998-01-09

2001-11-06

Brown, Glenn W. (Department: 2858)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C326S045000, C326S131000, C326S038000, C326S039000

Reexamination Certificate

active

06314549

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to circuit design methods for programmable logic arrays, and more particularly to power saving methods for programmable logic arrays. Programmable logic array (PLA) circuits and gate array (GA) logic circuits are the most common building modules for integrated circuit (IC) logic products. After IC designers describe logic operations by hardware description language (HDL), computer aid design (CAD) tools automatically translate the HDL into PLA or gate array circuits. These two methods (PLA or GA) are exchangeable. Most of logic circuits can be implemented by either way. PLA CAD tools combine all the logic relationships between a large number of input and output signals into one large group of AND operations followed by one large group of OR operations, and represent those operations by arrays of programmable connections. The physical structure of a PLA is highly regular, and its timing is easily predictable. On the contrary, gate array CAD tools break down complex logic calculations into series of single step logic operations such as NAND, NOR, INVERT, and implement those logic operations by a large number of logic gates. Such procedure is called “synthesizing” in the art. The physical structures of GA logic circuits are nearly random. That is why they are often called “random logic circuits” in the art. It usually requires very complex connections between logic gates. As IC fabrication technologies progressed into deep sub-micron, the resistance of conductor lines and the coupling capacitors between conductors became significant. The complex connections in GA logic circuits make timing calibration and performance optimization very difficult even with the helps of the most advanced CAD tools. It is expected that future IC technologies will not be able to improve circuit performance by reducing transistor dimensions due to the resistance and capacitor (RC) of conductor lines. On the other hand, PLA adapts better for the RC problem in advanced IC technologies due to its regular structures. The limitation for PLA comes from its power consumption. PLA consumes much more power than GA. Power requirement makes it nearly impossible to implement a large logic circuit completely by PLA.
Before the invention itself is explained, a typical prior art PLA is first explained to facilitate the understanding of the invention. FIG.
1
(
a
) is a schematic diagram showing the function and geometry of a prior art PLA. This PLA contains two programmable diode arrays (
102
,
103
). The first diode array (
102
) is called the “AND array” of the PLA because its function is to execute logic AND operations of its inputs. This AND array (
102
) contains (J+
1
) pairs of input lines (I
0
, I
0
#, I
1
, I
1
#, . . . , Ij, Ij#, . . . , IJ, IJ#), and (K+
1
) output lines (A
0
, A
1
, . . . , Ak, . . . , AK), where j, J, k and K are integers. Diodes (
100
) are selectively connected between the AND array input lines and the AND array output lines to control its logic functions. For the example in FIG.
1
(
a
), A
0
is connected to I
0
, I
1
#, and IJ# through diodes. If any one of the connected signals (I
0
, I
1
#, IJ#) are low, A
0
will be low. On the other word, A
0
=I
0
*I
1
#*IJ#, where “*” represents logic AND operation. For another example, Ak is connected to I
1
and IJ# through diodes so that Ak=[I
1
*IJ#], . . . etc.
The second diode array (
103
) of the PLA is called the “OR array” because its function is to execute logic OR operations. This OR array comprises (K+
1
) input lines (A
0
′, A
1
′, . . . Ak′, . . . , AK′), and (M+
1
) output lines (R
0
, R
1
. . . , Rm, . . . , RM), where k, K, m and M are integers. Diodes (
109
) are selectively connected between the OR array input lines and the OR array output lines to control its logic functions. For the example in FIG.
1
(
a
), R
0
is connected to A
0
′, A
1
′, and Ak′through diodes. If any one of the connected signals (A
0
′, A
1
′, Ak′) are high, R
0
will be high. On the other word, R
0
=[A
0
′+A
1
′+Ak′], where “+” represents logic OR operation. RM is connected to A
1
′, Ak′and AK′through diodes so that RM =[A
1
′+Ak′+AK′], . . . etc. The horizontal lines of the AND array and OR array represent intermediate logic terms called “minterms” in the art.
This PLA has (J+
1
) external input signals (IN
1
, IN
2
, . . . , INj, . . . , INJ), where j and J are integers. Each input signal is connected to one PLA input circuitry (
105
). Details of the PLA input circuitry (
105
) are shown in FIG.
1
(
b
). For the example, the j′th PLA input signal (INj) is connected to an inverter (
121
) to generate an inverted signal INj# that is connected to the gate of an n-channel transistor (MN
1
). The source of MN
1
is connected to the drain of another n-channel transistor (MN
3
). The drain of MN
1
is connected to one PLA AND array input signal (Ij), that is also connected to the drain of a p-channel transistor (MP
1
). The source of MP
1
is connected to power supply voltage Vcc. The gate of MP
1
is connected to pre-charge signal PG#, that is also connected to the gate of MN
3
. The source of MN
3
is connected to ground. The signal INj# is inverted by an inverter (
122
) before it is connected to the gate of an n-channel transistor (MN
2
). The source of MN
2
is connected to the drain of another n-channel transistor (MN
4
). The drain of MN
2
is connected to the other PLA AND array input signal (Ij#), that is also connected to the drain of a p-channel transistor (MP
2
). The source of MP
2
is connected to Vcc, while the gate of MP
2
is connected to the pre-charge signal PG#. The gate of MN
4
is also connected to PG#. The source of MN
4
is connected to Vss. When the PLA is idle, PG# is low, and both Ij and Ij# are pulled to power supply voltage Vcc. When the PLA is activated by pulling PG# high, Ij and Ij# are activated; if INj is high, Ij# is driven to ground voltage Vss while Ij is at high impedance state; if INj is low, Ij is driven to Vss while Ij# is at high impedance state. Referring back to FIG.
1
(
a
), paired input signals are connected to vertical input lines (I
0
, I
0
#, I
1
, I
1
#, . . . , Ij, lj#, . . . , IJ, IJ#) of the AND array (
102
). These AND array input lines intersect horizontal AND array output lines (A
1
, A
2
, . . . , Ak, . . . , AK). At idle state, these horizontal lines (A
1
, A
2
, . . . , Ak, . . . , AK) of the AND array are pre-charged to Vcc using p-channel transistors (
104
) controlled by pre-charge signal PG#. The signal PG# is also connected to a delay circuit (
108
) to generate OR array pre-charge signals (PG, PG
1
#). FIG.
1
(
c
) shows the structures of the delay circuit (
108
). A programmable delay circuitry (
125
) provides proper delay time, and the output of the delay circuit is connected to an inverter (
126
) to generate signal PG that is also connected to another inverter (
127
) to generate signal PG
1
#. These OR array pre-charge signals (PG, PG
1
#) control the data converters (
107
) between AND array and OR array. The structure of the data converter (
107
) is shown in FIG.
1
(
d
). The k′th AND array output signal (Ak) is inverted by an inverter (
123
) before connected to the gate of a p-channel transistor (MP
5
). The source of MP
5
is connected to PG
1
#, while its drain is connected to corresponding OR array input line (Ak′). Signal Ak′ is also connected to the drain of an n-channel transistor (MN
5
). The gate of MN
5
is connected to PG, while its source is connected to ground Vss. At idle state, PG
1
# is low and PG is high so that Ak′ is always driven to Vss. When the OR array (
103
) is activated, PG is low and PG
1
# is high; Ak&

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