Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-12-22
2001-02-20
Ghebretinsae, Temesghen (Department: 2734)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S376000, C327S157000, C327S158000
Reexamination Certificate
active
06192094
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a digital phase-frequency detector formed of two flip-flops generating digital output signals received by a charge pump. A feedback path formed of an AND gate and a delay device receives the digital output signals and generates a modified signal received by reset inputs of the two flip-flops.
Such a phase-frequency detector is used in a conventional digital phase-locked control loop. The digital phase-locked control loop includes three function modules, specifically a digital phase detector, an analog loop filter and a voltage-controlled oscillator (VCO) and optionally a frequency divider. The controlled variable in each phase-locked control loop is the phase angle.
The phase angle of a first ac signal is compared with the phase angle of a second ac signal. The phase difference between the two signals is determined in the control system and is used to synchronize the two signals.
In the known phase-locked control loop, one ac input signal, which is a reference signal of a given frequency, is compared with a controlled ac input signal of a variable frequency with the aid of the digital phase detector, which supplies a pulsed output current signal which depends on the phase difference between the two input signals.
The resulting output current signal is integrated over time in the analog loop filter, thus producing an output control voltage which actuates the voltage-control oscillator with regard to its frequency setting. The output signal of the voltage-controlled oscillator is the controlled signal, which is fed via the optionally provided frequency divider as the ac signal to the phase detector as one of the two input signals to be compared with regard to their phase angle.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a digital phase-frequency detector that overcomes the above-mentioned disadvantages of the prior art devices of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a digital phase-frequency detector for generating a pulsed output current. signal dependent on a phase difference between two ac input signals, including;
a first flip flop circuit having a reset input, a set input being fed one of the two ac input signals, and an output outputting digital output pulses that can be tapped as a function of a circuit state of the first flip-flop circuit;
a second flip-flop circuit having a reset input, a set input being fed another one of the two ac input signals, and an output outputting digital output pulses that can be tapped as a function of a circuit state of the second flip-flop circuit;
an AND logic circuit receiving the digital output pulses of the first and the second flip flop circuits and having an output outputting modified digital output pulses;
a delay device receiving the modified digital output pulses from the AND logic circuit and outputting a delay device signal received by the reset inputs of the first and second flip-flop circuits, the delay device increases a minimum duration of the modified digital output pulses by an anti-backlash pulse width given a presence of small phase differences between the two ac input signals, the delay device having a first delay path and a second delay path disposed parallel to one another, the first delay path assigned to positive edges of the modified digital output pulses coming from the output of the AND logic circuit and having a delay time unchanged by comparison with an original delay time, that is to say has a duration of the anti-backlash pulse, the second delay path assigned to negative edges of the modified digital output pulses coming from the output of the AND logic circuit and delays the negative edges by a delay time dimensioned to be only so long that the first and second flip-flop circuits being reliably reset; and
a charge pump formed of two switchable current sources, including a first current source and a second current source, the first current source supplying a first predetermined current in dependence on the digital output pulses of the first flip-flop circuit, and the second current source draws a second predetermined in dependence on the digital output pulses current from the second flip-flop circuit and the first and second predetermined currents form the pulsed output current signal in a ternary shape in a temporal variation.
It is the object of the invention to specify measures by which the disturbing waste time of the digital phase-frequency detector operating with anti-backlash pulses is shortened so that a digital phase-locked control loop fitted with such a phase-frequency detector has an improved settling response. The waste time of the digital phase-frequency detector with anti-backlash pulses is yielded in general from three components, specifically from the duration of the anti-backlash pulse, from the sum of the gate transit times between the digital output pulse states UP=DN=1 and the cancellation of the RESET and from the duration of the RESET pulse.
The duration of the anti-backlash pulse is fixed by the time which is required in order to represent the anti-backlash pulse (digital output pulses, the current source and the current sink in the charge pump) completely with rising edge, adequate settling phase and falling edge.
It is true that for a given circuit topology, this duration is determined by the technology and cannot be further shortened, The sum of the gate transit times between the digital output pulse states UP=DN=1 and the cancellation of the RESET can indeed be shortened by using fast logic blocks and an optimized circuit topology. By contrast, the measures specified by the invention amount to a reduction in the RESET pulses.
It is important in this case that, just as in the prior art, the RESET is applied with a delay upon the transition of the digital output pulse UP,DN→logic state “1”, in order to set the width of the anti-backlash pulse, but that upon the transition of the digital output pulse UP,DN→logic state “0” the delay time specified by the actual delay path is circumvented, in order as quickly as possible to cancel the RESET and thus to shorten the waste time of the digital phase-frequency detector.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a digital phase-frequency detector, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
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patent: 4322643 (1982-03-01), Preslar
patent: 4378509 (1983-03-01), Hatchett et al.
patent: 5805002 (1998-09-01), Ruetz
patent: 5892380 (1999-04-01), Quist
patent: 6100721 (2000-08-01), Durec et al.
patent: 3116603C2 (1990-12-01), None
Herrmann Helmut
Herzinger Stefan
Ghebretinsae Temesghen
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
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