Method of forming a contact hole in a semiconductor wafer

Details Method of forming a contact hole in a semiconductor wafer Method of forming a contact hole in a semiconductor wafer

2000-01-10

2001-10-02

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S398000

Reexamination Certificate

active

06297139

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of forming a shrunk contact hole in a semiconductor wafer, and more particularly, to a method of forming a contact hole of a DRAM (dynamic random access memory) on a semiconductor wafer.
DESCRIPTION OF THE PRIOR ART
Dynamic random access memory (DRAM) is a collection of a large number of DRAM cells. Each of the cells has a metal oxide semiconductor (MOS) transistor in series with a capacitor. In order to electrically connect a drain of a MOS transistor to a storage node of the capacitor, a node contact is formed by filling doped polysilicon into a contact hole. This node contact enables the reading and writing of data that is electrically stored in the capacitor. Because the size of the contact hole affects the size of a memory cell and a logical circuit, forming a contact hole with a smaller size than the photoresist pattern is thus a field of considerable importance to DRAM manufacturers.
Please refer to
FIG. 1
to FIG.
6
.
FIG. 1
to
FIG. 6
are cross-sectional diagrams of forming a shrunk contact hole
38
on a semiconductor wafer
10
according to the prior art. The semiconductor wafer
10
comprises a silicon substrate
12
, a doped area
14
positioned in a predetermined area of the silicon substrate
12
, a silicide layer
16
positioned on the surface of the doped area
14
, a gate
18
positioned on the surface of the silicon substrate
12
and a dielectric layer
24
formed of silicon oxide on the surface of the silicon substrate
12
, as shown in FIG.
1
. Each gate
18
comprises a silicon nitride spacer
22
on each of two opposite walls, and a silicon nitride passivation layer
20
on the top surface of the gate
18
. The doped area
14
serves as a conductive layer, such as the drain or the source of a MOS transistor, and the silicide layer
16
is used to reduce the contact resistance between the subsequently formed node contact and the drain or the source of the MOS transistor.
According to the prior art, an LPCVD (low pressure chemical vapor deposition) process is performed to deposit a polysilicon layer
26
uniformly on the surface of the dielectric layer
24
, as shown in
FIG. 2. A
spin coating process is then performed to form a photoresist layer
28
on the surface of the polysilicon layer
26
, and a lithographic process is performed to form a pattern
30
in the photoresist layer
28
, as shown in FIG.
3
. An anisotropic etching process is performed to remove the polysilicon layer
26
under the pattern
30
down to the surface of the dielectric layer
24
. A photoresist stripping process is then performed to totally remove the photoresist layer
28
so as to form an opening
32
in the polysilicon layer
26
, as shown in FIG.
4
. During the LPCVD process, the reactive temperature is kept between 600~650° C., and the reactive pressure is kept between 0.3~0.6 (torr).
An LPCVD process and a back etching process are performed to form a spacer on the interior walls of the opening
32
, as shown in
FIG. 5. A
dry etching process is then performed to remove the dielectric layer
24
between the spacers
36
down to the surface of the silicide layer
16
so as to form a contact hole
38
, as shown in FIG.
6
. During the dry etching process, the polysilicon layer
26
and the spacer
36
serve as a hard mask, and the etching selectivity is controlled to remove the silicon oxide faster than the polysilicon.
As the design rule of semiconductor fabrication shrinks, the diameter of the contact hole
38
reduces to 0.15 &mgr;m, but the depth of the contact hole
38
still remains between 6~10 kÅ. During the lithographic process to form the pattern
30
, the diameter of the pattern
30
on the photoresist layer
28
is limited to about 0.22 &mgr;m by the resolution limit of the optical exposure tool. In order to improve the limit of the lithographic process, a deposition and a back etching process are used to form the spacer
36
to reduce the diameter of the opening
32
so as to form the contact hole
38
with a smaller diameter.
The thickness of the spacer
36
is not uniform and changes with height, meaning that the thickness
35
is smaller than the thickness
37
. As the spacer
36
becomes thinner during the dry etching process, the diameter of the formed contact hole
38
becomes larger than the original design size. This can lead to inadvertent etching of the passivation layer
20
and the spacer
22
, causing them to be partially removed. This, in turn, leads to a shorter distance between the gate
13
and the conductive material subsequently filled into the contact hole
38
, which causes electrical leakage and even short circuiting.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of forming a shrunk contact hole of a DRAM on a semiconductor wafer.
In a preferred embodiment, the present invention provides a method of forming a shrunk contact hole on a semiconductor wafer. The semiconductor wafer comprises a substrate, a conductive layer positioned in a predetermined area on the substrate, a dielectric layer positioned on the surface of the substrate and covering the conductive layer, the method comprising:
forming an amorphous silicon (&agr;-Si) layer with an opening on the surface of the dielectric layer wherein the opening is positioned directly above the conductive layer and penetrates to the surface of the dielectric layer;
forming a polysilicon layer uniformly on the surface of the amorphous silicon layer;
performing a dry etching process to form a contact hole in the dielectric layer, the amorphous silicon layer and the polysilicon layer being used as a hard mask, the contact hole penetrating through the dielectric layer down to the surface of the conductive layer.
It is an advantage of the present invention that a single step HSG (hemi-spherical grain) process with selective growth properties according to the present invention replaces the dual step deposition and back etching process of the prior art. The present invention uses the HSG process to form a polysilicon layer with uniform thickness on the interior walls so as to reduce the diameter of the opening, improving the resolution limit of the lithographic process. Because the present invention uses the single step HSG process to replace the dual step deposition and back etching process, the cost of forming the contact hole is reduced. The present invention not only improves the resolution limit to satisfy design rule, but also reduces the cost of forming the contact hole.


REFERENCES:
patent: 5679608 (1997-10-01), Cheung et al.
patent: 5907782 (1999-05-01), Wu
patent: 6027967 (2000-02-01), Parekh et al.

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