Electrical computers and digital processing systems: processing – Processing control – Mode switch or change
Reexamination Certificate
1998-12-15
2001-10-16
Treat, William M. (Department: 2783)
Electrical computers and digital processing systems: processing
Processing control
Mode switch or change
C712S033000, C712S035000, C712S043000, C712S244000
Reexamination Certificate
active
06304958
ABSTRACT:
BACKGROUND OF THE INVENTION
In order to improve the operating performance, there is in the prior art a one-chip microcomputer which has a multiply and accumulation unit mounted thereon for executing a specific operation with a smaller cycle number. On the so-called “RISC processor”, as described on pp. 99 to 112 of Nikkei Electronics published on Nov. 23, 1992, there is mounted a multiply and accumulation module in addition to the general-purpose CPU so that the multiply and accumulation operations to be frequently executed in the digital signal processing may be executed in a smaller number of cycles.
For the higher performance, moreover, there is an example which is equipped with the multiply and accumulation unit capable of executing a plurality of identical operations simultaneously in parallel.
An example of Japanese Patent Laid-Open No. 83624/1994 is equipped with first and second execution lines which have a set of a data memory and an execution unit so that they can be simultaneously processed and independently processed, if necessary, with control signals coming from an instruction decoder.
In another publication of Japanese Patent Laid-Open No. 282926/1991, a floating point operation unit is provided as the data operation module so that the individual functions of the single-precision data operation/double-precision data operation/single-precision two-parallel data operation are realized with a common execution unit by switching modes.
In still another publication of Japanese Patent Laid-Open No. 94328/1991, the multiplier is exemplified by realizing the individual functions of the single-precision data operation/double-precision data operation/single-precision two-parallel data operation with a common hardware.
The techniques, as disclosed in the above-specified three Laid-Opens, are intended to improve the performance while suppressing the enlarged scale of the hardware by realizing the single-precision data operation and the single-precision two-parallel data operation by the common hardware.
SUMMARY OF THE INVENTION
In the invention disclosed in Japanese Patent Laid-Open No. 83624/1994, however, the first execution line and the second execution line are made independent so that the data of the first data memory cannot be executed by the second execution unit. Nor can be executed the data of the second data memory by the first execution unit. On the other hand, the remaining two Laid-Opens have disclosed means for the single-precision two-parallel data operation but not means for feeding source data necessary for the operations and specific means for storing the operation result in the memories.
In the inventions disclosed in the three Laid-Opens, therefore, the data transfer is obstructed to raise a problem in feeding the source data necessary for the operations to the execution means without fail so that the parallel operations of the microcomputer having the SIMD (Single Instruction Multiple Data) type parallel operation functions cannot be exhibited to the maximum. For the data transfer, on the other hand, it is important to retain the consistency on the instruction lines between the single operations and the parallel operations.
It is, therefore, an object of the invention to provide a microcomputer for feeding the source data necessary for operations without any delay while retaining the consistency on instruction lines between the ordinary single operations and the SIMD type parallel operations.
Here will be summarized the representatives of the invention to be disclosed herein.
According to the invention, there is provided a microcomputer comprising: a central processing unit including an address generating unit; a first memory and a second memory adapted to be individually fed with a common address from the address generating unit; a first execution unit coupled to the first memory and the second memory; and a second execution unit coupled to the first memory and the second memory and mounted together with the central processing unit, the first memory, the second memory and the first execution unit on a common semiconductor substrate, wherein the microcomputer is provided with: a first operating mode, in which data are fed from one of the first and second memories to the first execution unit and in which the first execution unit executes the operations whereas the second execution unit interrupts the operations; and a second operating mode, in which the data are fed from the first memory to the first execution unit and fed from the second memory to the second execution unit and in which the first execution unit and the second execution unit execute the operations.
According to the above-specified means, in the first operating mode, the data are fed from one of the first and second memories to the first execution unit, and the first execution unit executes the operations whereas the second execution unit interrupts the operations, so that the single operation can be executed. With the two memories for feeding the data to the execution unit, moreover, the amount of the data to be handled by the execution unit can be doubled from that of the prior art using memories of an equal degree of integration.
In the second operating mode, the data are fed from the first memory to the first execution unit and fed from the second memory to the second execution unit, and the first execution unit and the second execution unit execute the operations, so that a plurality of parallel operations can be executed. In this case, the first memory and the second memory can be accessed to with one address.
In a more specific memory construction, the first memory and the second memory may be switched to be address-mapped to different spaces in the first operating mode to identical spaces in the second operating mode.
In this case, in the first operating mode, the first memory and the second memory are address-mapped to the different spaces so that the data corresponding to the address in consideration are present in one of the first memory and the second memory and fed to the first execution unit. In the second operating mode, on the other hand, the first memory and the second memory are address-mapped to the identical spaces so that the data corresponding to the address in consideration are individually present in the first memory and the second memory and fed from the first memory to the first execution unit and from the second memory to the second execution unit.
There are a variety methods for switching the address mapping of the memories for the operating modes, but the following means can be specifically conceived.
As the construction of the memories, more specifically; each of the first memory and the second memory includes an address decoder and a control unit; the common address to be fed to the first memory and the second memory is composed of a plurality of bits, a portion of which are partially inputted to the control units and the remaining one of which are inputted to the address decoders; in the first operating mode, one of the first memory and the second memory is selected on the basis of the portion of bits; the control unit contained in the selected memory feeds the data corresponding to the remaining bits; and in the second operating mode, the data corresponding to the remaining bits are fed from the first memory and the second memory.
In the above-specified means, in the first operating mode, one of the first memory and the second memory is selected on the basis of the portion of bits so that the data corresponding to the remaining bits are outputted only from the selected memory. In the second operating mode, on the other hand, the selection of the memories on the portion of bits is not made, but the data corresponding to the remaining bits are outputted individually from the first memory and the second memory. Thus, it is possible to switch the address mappings of the memories for the operating modes. The aforementioned portion of bits are specified by a more significant 1 bit of the address but may be either a less significant 1 bit or another bit and can na
Kiuchi Atsushi
Nakagawa Tetsuya
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Treat William M.
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