Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-08-28
2001-11-27
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S401000, C257S622000
Reexamination Certificate
active
06323524
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed generally to semiconductor devices and to a method of manufacture thereof and, more particularly, to fabrication of semiconductor devices having vertically formed active regions.
BACKGROUND OF THE INVENTION
Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One such silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor. The MOS transistor is used as one of the basic building blocks of most modern electronic circuits.
The principal elements of a typical MOS semiconductor device are illustrated in FIG.
1
. The device generally includes a semiconductor substrate
101
on which a gate electrode
103
is disposed. The gate electrode
103
acts as a conductor. An input signal is typically applied to the gate electrode
103
via a gate terminal (not shown). Heavily doped source/drain regions
105
are formed within the semiconductor substrate
101
and are connected to source/drain terminals (not shown). As illustrated in
FIG. 1
, the typical MOS transistor is symmetrical, which means that the source and drain are interchangeable. Whether a region acts as a source or drain depends on the respective applied voltages and the type of device being made (e.g., PMOS, NMOS, etc.). Thus, as used herein, the term source/drain region refers generally to an active region used for the formation of a source or drain.
A channel region
107
is formed in the semiconductor substrate
101
beneath the gate electrode
103
and separates the source/drain regions
105
. The channel is typically lightly doped with a dopant of a type opposite to that of the source/drain regions
105
. The gate electrode
103
is generally separated from the semiconductor substrate
101
by an insulating layer
109
, typically an oxide layer such as SiO
2
. The insulating layer
109
is provided to prevent current from flowing between the gate electrode
103
and the source/drain regions
105
or channel region
107
.
In operation, an output voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode
103
, a transverse electric field is set up in the channel region
107
. By varying the transverse electric field, it is possible to modulate the conductance of the channel region
107
between the source region and the drain region. In this manner, an electric field controls the current flow through the channel region
107
. This type of device is commonly referred to as a MOS field-effect-transistor (MOSFET).
Semiconductor devices, like the one described above, are used in large numbers to construct most modern electronic devices. As a larger number of such devices are integrated into a single wafer, improved performance and capabilities of electronic devices can be achieved. In order to increase the number of semiconductor devices which may be formed on a given surface area of a substrate, the semiconductor devices must be scaled down (i.e., made smaller). This is typically accomplished by reducing the lateral dimensions of the device structure. Continued efforts to reduce the dimensions of the semiconductor devices encounter problems related to device performance. Thus, there generally exist a tension between desires to further scale down the semiconductor devices and the need to maintain high performance and reliability.
SUMMARY OF THE INVENTION
Generally, the present invention relates to a semiconductor device and fabrication process in which devices are formed having vertical active regions. In accordance with one embodiment of the invention, a semiconductor device is formed by forming a trench within a substrate. An oxide layer is formed within the trench and portions of the oxide layer are removed to expose one or more portions of the substrate within the trench. A plurality of doped polysilicon pillars are formed within the trench. The doped polysilicon pillars include one or more active region pillars formed on the one or more exposed portions of the substrate.
In accordance with another embodiment of the invention, a semiconductor device is provided. The semiconductor device includes a substrate having a trench formed therein and at least one vertical source/drain region formed within the trench. The vertical source/drain region includes a doped polysilicon pillar as well as a doped region of the substrate.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.
REFERENCES:
patent: 4016587 (1977-04-01), De La Moneda
patent: 4689871 (1987-09-01), Malhi
patent: 4803176 (1989-02-01), Bower
patent: 4903108 (1990-02-01), Young et al.
patent: 4933733 (1990-06-01), Iranmanesh et al.
patent: 4952993 (1990-08-01), Okumura
patent: 5043778 (1991-08-01), Teng et al.
patent: 5285093 (1994-02-01), Lage et al.
patent: 5352915 (1994-10-01), Hutchings et al.
patent: 5430673 (1995-07-01), Hong et al.
patent: 5457070 (1995-10-01), Hirade
patent: 5512517 (1996-04-01), Bryant
patent: 5563080 (1996-10-01), Ahn
patent: 5844274 (1998-12-01), Tsutsumi
patent: 5846862 (1998-12-01), May et al.
patent: 196 15 692 A1 (1997-02-01), None
patent: 0 299 505 A2 (1989-01-01), None
patent: 0 766 306 A1 (1997-04-01), None
patent: 57-097672 (1982-06-01), None
patent: 57141968 (1982-09-01), None
patent: 60103671 (1985-06-01), None
Dawson Robert
May Charles E.
Advanced Micro Devices , Inc.
Prenty Mark V.
LandOfFree
Semiconductor device having a vertical active region and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having a vertical active region and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having a vertical active region and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2610054