Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-05-17
2001-02-27
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S334000, C257S368000, C257S369000, C257S371000, C257S372000, C257S903000
Reexamination Certificate
active
06194765
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to an integrated electrical circuit having at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters which are electrically connected to one another, the inverters each contain two complementary MOS transistors having a source, a drain and a channel, and the channels of the complementary MOS transistors have different conductivity types.
A static semiconductor memory cell of this type is preferably configured as a bistable flip-flop. The flip-flop has two stable states. Memory cells of this type are distinguished by their short access time, which is of the order of magnitude of a few ns.
Furthermore, the memory cell can be integrated into a CMOS basic process by which the integrated electrical circuit is fabricated. In order to enable random access, the memory cell also contains two bit lines and a word line in addition to the two terminals necessary for the application of an electrical potential. A memory cell of this type is referred to as static random access memory (SRAM).
The static memory cell can be realized in the CMOS basic process without additional process steps. Therefore, it can also be integrated into complex logic circuits such as microprocessors. However, it is likewise possible to construct a memory cell configuration with memory cells of this type. It is also possible to replace DRAMs with SRAMs of this type, and this is advantageous owing to the shorter access time and also owing to the lower activation power.
One disadvantage of SRAMs is the large area that they occupy. Given a minimum feature size F, the memory typically taken up per memory cell is 8 F
2
in the case of DRAMs, 60 F
2
in the case of SRAMs with a 6-transistor cell or 45 F
2
in the case of SRAMs with a cell formed from four transistors and, in addition, two thin film transistors (TFT). A TFT is a MOS transistor with a channel region made of polycrystalline silicon that can be disposed above other transistors.
The minimum feature size F is preferably of the order of magnitude of 0.1 um to 0.5 um, values of 0.18 um to 0.35 um being preferred. However, it is foreseeable that this feature size will be able to be reduced further by a further development of the process technology, in particular of the photolithographic methods used.
Arranging TFTs above other transistors results in vertical integration, which reduces the area requirement. However, an area requirement of 45 F
2
remains considerably larger than the area occupation of 8 F
2
in the case of DRAMs. A solution to this disadvantage has not been disclosed to date.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated electrical circuit having at least one memory cell and a method for fabricating it which overcomes the above-mentioned disadvantages of the prior art devices and methods of this general type, in which the space requirement for the memory cell is as small as possible, and to specify a method for fabricating the integrated electrical circuit.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated electrical circuit, containing:
a semiconductor substrate having a surface;
a memory cell is disposed in a region of the surface of the semiconductor substrate and has inverters electrically connected to one another, the inverters each contain two complementary MOS transistors each having a source, a drain and a channel, and the channel of each of the two complementary MOS transistors have different conductivity types, the memory cell, including:
a first doped semiconductor layer disposed on the semiconductor substrate;
a second doped semiconductor layer disposed on the first doped semiconductor layer;
a third doped semiconductor layer disposed on the second doped semiconductor layer;
a fourth doped semiconductor layer disposed on the third doped semiconductor layer;
a fifth doped semiconductor layer disposed on the fourth doped semiconductor layer;
and a sixth doped semiconductor layer disposed on the fifth doped semiconductor layer, the first doped semiconductor layer, the second doped semiconductor layer, the third doped semiconductor layer, the fourth doped semiconductor layer, the fifth doped semiconductor layer and the sixth doped semiconductor layer define a layer sequence doped alternately with opposite conductivity types;
the layer sequence has a grid of rectangular trenches formed therein, the grid of rectangular trenches reaches down into the semiconductor substrate and the grid of rectangular trenches defines at least two layer assemblies each having side walls;
the at least two layer assemblies each have a further trench formed therein, the further trench reaches down into the third doped semiconductor layer and connects two mutually opposite rectangular trenches of the grid of rectangular trenches to one another in a respective layer assembly;
the inverters are disposed on mutually opposite side walls of the side walls of the at least two layer assemblies, the first doped semiconductor layer, the second doped semiconductor layer and the third doped semiconductor layer in each case forming the source, the channel and the drain of one of the two complementary MOS transistors of a respective inverter and the fourth doped semiconductor layer, the fifth doped semiconductor layer and the sixth doped semiconductor layer in each case form the source, the channel and the drain of another of the two complementary MOS transistors of the respective inverter;
two selection transistors each have a source, a channel and a drain and are disposed in each case on a side of the respective layer assembly which is remote from the inverters, the source, the channel and the drain of each of the two selection transistors are formed by the third doped semiconductor layer, the fourth doped semiconductor layer and the fifth doped semiconductor layer; and
the further trench disposed in the layer sequence in each case are formed between one of the two selection transistors and one of the inverters.
In the integrated electrical circuit, a first doped semiconductor layer, a second doped semiconductor layer, a third doped semiconductor layer, a fourth doped semiconductor layer, a fifth doped semiconductor layer and a sixth doped semiconductor layer are disposed one above the other on a semiconductor substrate and are each doped alternately by the opposite conductivity type. A grid of rectangular trenches which reach down into the semiconductor substrate is provided, which grid defines at least two layer assemblies. A further trench is provided in each case in each of the two layer assemblies, which further trench reaches down into the third doped semiconductor layer and connects two mutually opposite rectangular trenches to one another in the layer assembly. By virtue of the further trench, two separate layer stacks are realized in the layer assembly in the upper region, that is to say in the sixth doped semiconductor layer, fifth doped semiconductor layer, fourth doped semiconductor layer and part of the third doped semiconductor layer.
The circuit contains two inverters that are disposed on mutually opposite side walls of the two layer assemblies. Each of the inverters has a transistor and a transistor that is complementary thereto. The first doped semiconductor layer, the second doped semiconductor layer and the third doped semiconductor layer in each case form the source, the channel and the drain of the transistor and the fourth doped semiconductor layer, the fifth doped semiconductor layer and the sixth doped semiconductor layer form the source, the channel and the drain of the transistor which is complementary thereto. Furthermore, two selection transistors are provided, which are disposed in each case on that side of the respective layer assembly which is remote from the inverter, the source, the channel and the drain of the selection transistors are formed by the th
Franosch Martin
Gruning Ulrike
Lehmann Volker
Reisinger Hans
Schafer Herbert
Greenberg Laurence A.
Lerner Herbert L.
Ortiz Edgardo
Saadat Mahshid
Siemens Aktiengesellschaft
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