Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
1999-09-23
2001-11-20
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S302000
Reexamination Certificate
active
06319798
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor fabrication, and more particularly to methods for fabricating improved ultra-large scale integration (ULSI) semiconductor devices such as ULSI metal oxide silicon field effect transistors (MOSFETs).
BACKGROUND OF THE INVENTION
Semiconductor chips are used in many applications, including as processor chips for computers, and as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
A common circuit component of semiconductor chips is the transistor. In ULSI semiconductor chips, a transistor is established by forming a polysilicon gate on a silicon substrate, and then forming a source region and a drain region in the substrate beneath the gate by implanting appropriate dopant materials into the areas of the substrate that are to become the source and drain regions. The gate is insulated from the substrate by a thin gate oxide layer, with small portions of the source and drain regions, referred to as “extensions”, extending toward and virtually under the gate.
Between the source and drain regions and under the gate oxide layer is a source/drain extension (SDE) region, which is doped. The SDE region typically is doped early in the fabrication process, with the SDE dopant usually being implanted during the steps of forming the gate and source and drain regions. This generally-described structure cooperates to function as a transistor.
To suppress deleterious “short channel” effects such as threshold voltage roll-off (i.e., transistor operation at below intended voltages), it is important that the lateral dopant profile of the source/drain extensions be steep. Stated differently, it is important that virtually all of the dopant be concentrated within a relatively small area that is to function as the source/drain extension, with little or no dopant being located outside this relatively small doped region.
The present invention recognizes that the dopant gradient is deleteriously affected by high thermal budgets and particularly by high temperatures, such as those typically required during annealing to activate the dopant. Stated differently, exposing dopant in a source/drain extension to high temperatures can cause the dopant to thermally diffuse and, hence, can cause the dopant profile undesirably to spread. Nonetheless, the dopant must be activated for the device to function properly. The present invention has considered the above problem and has provided the solutions disclosed herein.
BRIEF SUMMARY OF THE INVENTION
A method for establishing at least one transistor on a semiconductor device includes providing a semiconductor substrate, and implanting deep dopants into the substrate to establish a source region and a drain region. Then, the method includes heating the substrate to activate the deep dopants. After activation, a neutral ion species is implanted in the substrate between the source and drain regions to define an amorphous extension region. Also, a source/drain extension (SDE) dopant is implanted in the amorphous extension region and is activated by heating the amorphous extension region.
In a preferred embodiment, the substrate is heated to more than nine hundred fifty degrees Celsius (950° C.) to activate the deep dopants, and the amorphous extension region is heated to no more than nine hundred fifty degrees Celsius (950° C.), and more preferably is heated to no more than six hundred fifty degrees Celsius (650° C.). With this process, the SDE dopant is substantially not thermally diffused.
As disclosed in greater detail below, the substrate defines a surface, and the neutral ion species preferably is implanted in the substrate by directing a beam of the neutral ion species onto the surface at an oblique angle to the surface. If desired, a halo dopant can also be implanted in the amorphous extension region. The amorphous extension region defines a depth, and the halo dopant is implanted to a halo depth of about one-half the depth of the amorphous extension region, with the SDE dopant in turn being implanted to a depth of about one-half the halo depth.
In another aspect, a method for making an ultra-large scale integration (ULSI) semiconductor device includes forming source and drain regions in a semiconductor substrate using a first activation temperature, then forming a doped source/drain extension (SDE) region between the source and drain regions using a second activation temperature less than the first activation temperature.
In yet another aspect, a semiconductor device includes a semiconductor substrate, at least one transistor gate on the substrate, and source and drain regions in the substrate below the gate. A source/drain extension (SDE) region is located between the source region and the drain region under the gate, and a recrystallized preamorphization substance is in the SDE extension region.
Other features of the present invention are disclosed or apparent in the section entitled “DETAILED DESCRIPTION OF THE INVENTION”.
REFERENCES:
patent: 5970353 (1999-10-01), Sultan et al.
patent: 6008099 (1999-12-01), Sultan et al.
patent: 6180464 (2001-01-01), Krivokapic et al.
patent: 6218250 (2001-04-01), Hause et al.
Advanced Micro Devices , Inc.
LaRiviere Grubman & Payne, LLP
Le Dung A
Nelms David
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